The user can refer to the “ TRANSCEIVER EVALUATION SOFTWARE (TES) OPERATION “ in the ADRV9026 user guide to know how to use GUI software generate the initialization configuration data. Some main item in the generated initialization configuration data file explained as below:
1. gpIntMaskPin0/ gpIntMaskPin1: This setting will disable/enable general purpose interrupt event each bit. When the selected bit set 1 will mask that bit corresponding interrupt event. Set as 0 will enable that bit corresponding interrupt event. The user can refer to the “ GP_INTERRUPT Bitmask Description ”table in the ADRV9026 user guide to know the description of the interrupt sources and their bit positions. Customer can select the events what they want to monitor. The user can put critical errors (PLL unlock, JESD link down, etc) on one GP_INT pin, and other errors, maybe like unexpected K characters or whatever, on the other GP_INT pin. Both GP_INT pins have identical functionality but allows customers to separate out "critical" interrupts from non-critical interrupts2. The rxDataFormat section in the configuration file just set up the Rx data format. The user can refer to the “ RECEIVER DATA FORMAT DATA STRUCTURE “ section in the ADRV9026 user guide to know each parameter meaning and how to configure it base on different application scenario. To the user want to use the ADRV9026 dynamic slicer feature. Leave the rxDataFormat section setting as default. Refer to the “ ADRV9026 Dynamic Slicer ”user guide in the ‘Documents’ section of the webpage ‘Design Support ADRV9026’ on engineering zone to know how to configure the dynamic slicer by API function. The user just need to call the API command adi_adrv9025_RxDynamicSlicerConfigSet() API function to enable and configure the dynamic slicer.3. The dacFullScale parameter in tx section will set the DAC full scale . When set this parameter as ADI_ADRV9025_TX_DACFS_3DB will increase the Tx output power by 3dB. If the user want to use the default Tx output power level. Set it as ADI_ADRV9025_TX_DACFS_0DB.4. The syncbInLvdsMode parameter in framer section will decide the Syncbin working mode. 1 = Enables LVDS input pad; 0 = enables CMOS input pad.5. The newSysrefOnRelink/ sysrefForStartup/ sysrefNShotEnable/ sysrefNShotCount/ sysrefIgnoreWhenLinked parameter in framer section is related with link setup. Refer to the “ JESD204B/JESD204C Framer Configuration Structure Member Description “ table in the ADRV9026 user guide to know each parameter meaning and select needed setting.6. The newSysrefOnRelink/ sysrefForStartup/ sysrefNShotEnable/ sysrefNShotCount/ sysrefIgnoreWhenLinked parameter in de-framer section is related with link setup Refer to the “ JESD204B/JESD204C DeFramer Configuration Structure Member Description “ table in the ADRV9026 user guide to know each parameter meaning and select needed setting.7. The highBoost parameter in desCfg data structure will decide the CTLE circuit gain at high frequency. If channel insertion loss is higher than 12dB then this parameter need to be set as 1. If the channel insertion loss is lower than 12dB then this parameter need to set as 0. The user can set this parameter base on their JESD lane insertion loss.8. The syncbOutLvdsMode parameter in de-framer section will decide the Syncbout working mode. 1 = Enables LVDS output pad; 0 = enables CMOS output pad.9. The singleChannel2PinModeLowOrxSel/ singleChannel2PinModeHighOrxSel parameter in adi_adrv9025_PostMcsInit_t data structure will decide the ORx path working mode. The user can refer to the “ adi_adrv9025_ORxRadioCtrlModeCfg_t Definition “ table in the ADRV9026 user guide know how to set these parameters. When singleChannel2PinModeHighOrxSel set as ADI_ADRV9025_SINGLE_CH_PIN_MODE_ORX2_FE. Selects ORx2 when the ORX_CTRL_B pin is high in single channel 2 pin ORx enable mode10. The streamGpioCfg section will configure the stream GPIO. To the Rx gain control mode switch GPIO. The user need to select the proper GPIO pin in stream setting tab(Rx Gain Gpio Pin dialog box) and generate the requested stream file and initialization configuration file.11. The auxPllFreq_Hz in adi_adrv9025_PostMcsInit_t data structure will set the AUXLO frequency. Need to consider the frequency delta to avoid the VCO pulling between AUXLO and RFLO.12. The calMask parameter in initCals section will decide what initialization calibration will be executed during chip bring up. The user can refer to the “ calMask Bit Assignments “ table in the ADRV9026 user guide to enable the needed initialization calibration. The default setting in current version software is 0xD37FF.