ADRV9026 external clock requirements

  • As per the ADRV9026 datasheet, ADI recommends to maintain the device clock (DEV_CLK+/-) V P-P signal level (differential) between 0.2V to 1V. This signal should be AC-coupled, the common-mode voltage is internally supplied. For optimal spurious performance and to meet the specified PLL performance parameters, ADI recommends to use a 1 V p-p input clock differential signal level.
  • The external clock inputs are connected to DEVCLK+ and DEVCLK− through AC coupling capacitors. A 100 Ω termination across the input near pins C8 and C9 is needed. ADI recommends to shield the clock traces by ground planes above and below with vias staggered along the edges of the differential pair routing. This shielding is important because it protects the reference clock inputs from spurious signals that can transfer to different clock domains within the device. Please refer to the ‘Synthesizer Configuration’ and ‘PCB LAYOUT CONSIDERATIONS’ section for additional details regarding routing/layout recommendations for the clock signals.