ADRV9010: Override FPGA side DFE LPM in PHY

Hi All,

I was doing JESD204B bring up in ADRV9010. I read the below ink and other related stuff. 


https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9010/f/q-a/542098/adrv9010-de-framer-link-set-up-procedure

I have few doubts in this. 

1) What is use of overriding FPGA side DFE LPM in PHY before sending SYSREF

2)  In the above link, we are using single shot SYSREF. Though, we should have minimum 3 clock pulses to sync various block of adrv9010 so how can single shot can sync various block? 

3) I have configured continuous SYSREF pattern instead of single shot so do I need to follow step (8)  of the above link ? 

Regards,

Manish



Indentation
[edited by: manish3134 at 1:04 PM (GMT -4) on 8 Jun 2021]
  • 0
    •  Analog Employees 
    on Jun 30, 2021 6:59 AM

    Q1: LPM mode is recommended for applications with line rates up to 11.2Gb/s for short reach applications, with channel losses of 12dB or less and DFE mode is recommended for medium to long reach applications, with channel losses of 8dB and above at the Nyquist frequency

    Q2: Above link talks about JESD bringup, 3 SYS REF are required during MCS phase and in SW, we are requesting multiple times till we get MCS status of 0x17. For JESD bringup, you can use Single shot or Continuous SYS REF.

    Q3: Not required.