ADRV9008 software

Refer to the below links for generating the files from the GUI:

 RE: ADRV9008-1 malfunction  

Refer to the below link for instruction son building with the generated files from GUI:

https://wiki.analog.com/resources/eval/user-guides/adrv9009/no-os-setup 

Hello srimoyi !

Thanks for you quick answer.

My colleague FPGA engineer configured the clock part with AD9528_GUI, and I was responsible for the.c part. Once I've determined the TTES_GUI parameters, I can use TTES_GUI to generate Init.c Files, It contains headless.c, headless.h, talise_config.c,talise_config.h, talise_config_ad9528.h, TaliseStream.bin.

I then replace the files in API/src/app/example with these files(TaliseStream.bin is not included), and compile the files containing the makefiles on linux using the make command. Is that right?

Also, something like "Insert User BBIC JESD204B Initialization Code here,"What is the initialization code I need to fill in?

aaa said:

I then replace the files in API/src/app/example with these files(TaliseStream.bin is not included), and compile the files containing the makefiles on linux using the make command. Is that right?

Yes correct. 

aaa said:

Insert User BBIC JESD204B Initialization Code here

You need  write the FPGA side JESD initialization code here. You need to configure the FPGA side JESD framers/deframers  Note that the JESD init parameters like L,M,N, lane rate etc  for the FPGA side  Framers/Deframers should be configured the same as that of the chip side framer/deframer parameters, for successful JESD initialization

aaa said:

I then replace the files in API/src/app/example with these files(TaliseStream.bin is not included), and compile the files containing the makefiles on linux using the make command. Is that right?

Yes correct. 

aaa said:

Insert User BBIC JESD204B Initialization Code here

You need  write the FPGA side JESD initialization code here. You need to configure the FPGA side JESD framers/deframers  Note that the JESD init parameters like L,M,N, lane rate etc  for the FPGA side  Framers/Deframers should be configured the same as that of the chip side framer/deframer parameters, for successful JESD initialization

Hello,srimoyi!

    Recently we are still debugging ADRV9008BBCZ-1. We use the GPIO of XC7Z045 to connect to the GPIO of XC7VX690T, ADRV9008 to connect to XC7VX690T, and configure the information of ADRV9008 by configuring the SPI of the PS end of XC7Z045. Namely XC7Z045(PS-SPI)→XC7Z045 (GPIO)→ XC7VX690T(SPI)→ ADRV9008. The EVALUATION BOARD PHOTOGRAPHS were not used.

    After the configuration was completed, we could not find the chip. The data sent by SPI could be written successfully, but could not be read. Is it necessary to use EVALUATION BOARD PHOTOGRAPHS? Can we access the ADRV9008 according to our hardware platform?

Hello,srimoyi!

    Recently we are still debugging ADRV9008BBCZ-1. We use the GPIO of XC7Z045 to connect to the GPIO of XC7VX690T, ADRV9008 to connect to XC7VX690T, and configure the information of ADRV9008 by configuring the SPI of the PS end of XC7Z045. Namely XC7Z045(PS-SPI)→XC7Z045 (GPIO)→ XC7VX690T(SPI)→ ADRV9008. The EVALUATION BOARD PHOTOGRAPHS were not used.

    After the configuration was completed, we could not find the chip. The data sent by SPI could be written successfully, but could not be read. Is it necessary to use EVALUATION BOARD PHOTOGRAPHS? Can we access the ADRV9008 according to our hardware platform?