ADRV9009 SYNCIN SYNCOUT length matching with DEVCLK/SYSREF

To maintain the deterministic latency across multiple devices it is recommended to have trace length matching for the SYSREF, device clock, and sync signals.

I think you are a little bit to quick with your answer... 

How shall I do that? Sysref and devclk are provided from an external PLL, and sync is connected from fpga to adrv9009?

We are drawing our own pcb based on fmcomms8, but we are not sure about the rules of the trace lengths of the syncin and syncout signals. 

adrv9009 operates in subclass 1 (from  adrv9009 UG-1295 hardware Reference manual)

from: JESD204B Survival Guide (analog.com)

It seems that the sync lines are used for state machine stuff UG-1295 

Make sure that setup and hold times of the DEVCLK and SYSREF should be length matched as in the  attached snippet . As SYSREF and DEVCLK are provided from an external PLL and sync is connected from FPGA to TRX its not required to have length matching between SYNC signals and DEVCLK/SYSREF.  .