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ADRV9009 ARM Initialization Sequence Abort

Category: Software
Product Number: ADRV9009
Software Version: API 3.6.2 Build 1, ARM Firmware 6.2.1

How do I determine why the ARM core is aborting an initialization sequence?

Error Message: "[ERROR](131084) HAL - Talise ARM initialization sequence aborted "

This is a custom board.  I am using the stream processor, arm firmware and configuration output from the TES gui.  I am able to get some initial calibrations to run, calibration mask 0x00000046 to be specific.  It seems that any calibration that uses the TX channels, aborts.

The Hardware Reference Manual (page 187), describes debugging of initial calibration errors when TALISE_waitInitCals() returns 0x07.  In my case TALISE_waitInitCals() returns 0x06.

The output of TALISE_getInitCalStatus() is below.  

calsSincePowerUp 0x00000002
calsLastRun 0x00000000 
calsMinimum 0x0004004f 
initErrCal 0x00
initErrCode 0x00 
talAction 0x00000000

Version Information:

Arm Version 6.2.1

API version 3.6.2 build 1

Product ID 1, Revision 12.0

  • Can you send us the profile that you are using  for loading into the TESGUI? Hope you have generated the profile from the Matlab based filter wizard tool and use as it is generated for loading into the TES GUI.

    If you disable, the TX related cals, is the initialization passing successfuuly?

  • taliseInit_t talInit =
    {
    	/* SPI settings */
        .spiSettings =
        {
    		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
    		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
    		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
    		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
    		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
    	},
    	
        /* Rx settings */
        .rx = 
        {
            .rxProfile =
            {
                .rxFir = 
                {
                    .gain_dB = -6,                /* filter gain */
                    .numFirCoefs = 48,            /* number of coefficients in the FIR filter */
                    .coefs = &rxFirCoefs[0]
                },
                .rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
                .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
                .rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
                .rxOutputRate_kHz = 245760,            /* Rx IQ data rate in kHz */
                .rfBandwidth_Hz = 200000000,    /* The Rx RF passband bandwidth for the profile */
                .rxBbf3dBCorner_kHz = 200000,    /* Rx BBF 3dB corner in kHz */
                .rxAdcProfile = {182, 142, 173, 90, 1280, 982, 1335, 96, 1369, 48, 1012, 18, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
                .rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
                .rxNcoShifterCfg =
                {
                    .bandAInputBandWidth_kHz = 0,
                    .bandAInputCenterFreq_kHz = 0,
                    .bandANco1Freq_kHz = 0,
                    .bandANco2Freq_kHz = 0,
                    .bandBInputBandWidth_kHz = 0,
                    .bandBInputCenterFreq_kHz = 0,
                    .bandBNco1Freq_kHz = 0,
                    .bandBNco2Freq_kHz = 0
                }
            },
            .framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
            .rxGainCtrl = 
            {
                .gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
                .rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
                .rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
                .rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
                .rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
                .rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
                .rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
            },
            .rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
        },
    
    
        /* Tx settings */
        .tx = 
        {
            .txProfile =
            {
                .dacDiv = 1,                        /* The divider used to generate the DAC clock */
                .txFir = 
                {
                    .gain_dB = 6,                        /* filter gain */
                    .numFirCoefs = 40,                    /* number of coefficients in the FIR filter */
                    .coefs = &txFirCoefs[0]
                },
                .txFirInterpolation = 1,                    /* The Tx digital FIR filter interpolation (1,2,4) */
                .thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
                .thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
                .thb3Interpolation = 2,                    /* Tx Halfband3 filter interpolation (1,2)*/
                .txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
                .txInputRate_kHz = 245760,                    /* Primary Signal BW */
                .primarySigBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
                .rfBandwidth_Hz = 225000000,            /* The Tx RF passband bandwidth for the profile */
                .txDac3dBCorner_kHz = 225000,                /* The DAC filter 3dB corner in kHz */
                .txBbf3dBCorner_kHz = 113000,                /* The BBF 3dB corner in kHz */
                .loopBackAdcProfile = {212, 140, 175, 90, 1280, 699, 1304, 59, 1343, 33, 913, 27, 48, 48, 34, 192, 0, 0, 0, 0, 48, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
            },
            .deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
            .txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
            .txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
            .tx1Atten_mdB = 0,                            /* Initial Tx1 Attenuation */
            .tx2Atten_mdB = 0,                            /* Initial Tx2 Attenuation */
            .disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
        },
    
    
        /* ObsRx settings */
        .obsRx = 
        {
            .orxProfile =
            {
                .rxFir = 
                {
                    .gain_dB = 6,                /* filter gain */
                    .numFirCoefs = 24,            /* number of coefficients in the FIR filter */
                    .coefs = &obsrxFirCoefs[0]
                },
                .rxFirDecimation = 1,            /* Rx FIR decimation (1,2,4) */
                .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
                .rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
                .orxOutputRate_kHz = 245760,            /* Rx IQ data rate in kHz */
                .rfBandwidth_Hz = 200000000,    /* The Rx RF passband bandwidth for the profile */
                .rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
                .orxLowPassAdcProfile = {185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
                .orxBandPassAdcProfile = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
                .orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
                .orxMergeFilter  = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
            },
            .orxGainCtrl = 
            {
                .gainMode = TAL_MGC,
                .orx1GainIndex = 255,
                .orx2GainIndex = 255,
                .orx1MaxGainIndex = 255,
                .orx1MinGainIndex = 195,
                .orx2MaxGainIndex = 255,
                .orx2MinGainIndex = 195
            },
            .framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
            .obsRxChannelsEnable = TAL_ORX1, /*TAL_ORXOFF,*/        /* The desired ObsRx Channels to enable during initialization */
            .obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
        },
    
        /* Digital Clock Settings */
        .clocks = 
        {
            .deviceClock_kHz = 122880,            /* CLKPLL and device reference clock frequency in kHz */
            .clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
            .clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
            .rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
            .rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
        },
    
        /* JESD204B settings */
        .jesd204Settings = 
        {
            /* Framer A settings */
            .framerA = 
            {
                .bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
                .M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
                .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
                .F = 4,                            /* F (number of bytes per frame) */
                .Np = 16,                            /* Np (converter sample resolution) */
                .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
                .externalSysref = 0,            /* 0=use internal SYSREF, 1= use external SYSREF */
                .serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
                .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
                .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbInSelect = 0,                /* syncbInSelect; */
                .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
                .syncbInLvdsMode = 1,
                .syncbInLvdsPnInvert = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Framer B settings */
            .framerB = 
            {
                .bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
                .M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
                .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
                .F = 4,                            /* F (number of bytes per frame) */
                .Np = 16,                            /* Np (converter sample resolution) */
                .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
                .externalSysref = 0,            /* 0=use internal SYSREF, 1= use external SYSREF */
                .serializerLanesEnabled = 0x04,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
                .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
                .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbInSelect = 1,                /* syncbInSelect; */
                .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
                .syncbInLvdsMode = 1,
                .syncbInLvdsPnInvert = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Deframer A settings */
            .deframerA = 
            {
                .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
                .M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
                .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
                .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
                .externalSysref = 0,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
                .deserializerLanesEnabled = 0x03,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
                .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
                .lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
                .Np = 16,                /* Np (converter sample resolution) */
                .syncbOutLvdsMode = 1,
                .syncbOutLvdsPnInvert = 0,
                .syncbOutCmosSlewRate = 0,
                .syncbOutCmosDriveLevel = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Deframer B settings */
            .deframerB = 
            {
                .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
                .M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
                .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
                .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
                .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
                .deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
                .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
                .lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
                .Np = 16,                /* Np (converter sample resolution) */
                .syncbOutLvdsMode = 1,
                .syncbOutLvdsPnInvert = 0,
                .syncbOutCmosSlewRate = 0,
                .syncbOutCmosDriveLevel = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            .serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
            .serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
            .serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
            .desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
            .desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
            .sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
            .sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
        }
    };

    I am able to run the cals 0x46 without error.  Any other calibrations and the Abort occurs.

    calsSincePowerUp 0x00000046                     
    calsLastRun 0x00000046                          
    calsMinimum 0x0004004f                          
    initErrCal 0x00                                 
    initErrCode 0x00                                
    talAction 0x00000000                            
    Temperature 45 C
    RX STATE:                                       
        RX 1 & 2 ON                                 
    TX STATE:                                       
        TX 1 & 2 ON                                 
    [?](0) HAL - TALISE_getPllsLockStatus()         
    CLK PLL is LOCKED                               
    RF PLL is LOCKED                                
    AUX PLL is LOCKED                               
    [?](0) HAL - TALISE_getGpIntStatus()            
                                                    
    Interrupt Status (0x00000000): 

    For the sake of others who read this, and clarity.   The calibration value I reference is a bit mask that enables the initialization calibrations.  The definition is below and defined in talise_cals_types.h.

        // TAL_TX_BB_FILTER            = 0x00000001,   /*!< Tx BB filter calibration */
        // TAL_ADC_TUNER               = 0x00000002,   /*!< ADC tuner calibration */
        // TAL_TIA_3DB_CORNER          = 0x00000004,   /*!< TIA 3dB corner calibration */
        // TAL_DC_OFFSET               = 0x00000008,   /*!< DC offset calibration */
        // TAL_TX_ATTENUATION_DELAY    = 0x00000010,   /*!< Tx attenuation delay calibration */
        // TAL_RX_GAIN_DELAY           = 0x00000020,   /*!< Rx gain delay calibration */
        // TAL_FLASH_CAL               = 0x00000040,   /*!< Flash converter comparator calibration */
        // TAL_PATH_DELAY              = 0x00000080,   /*!< Path delay equalization calibration */
        // TAL_TX_LO_LEAKAGE_INTERNAL  = 0x00000100,   /*!< Internal Tx LO leakage calibration */
        // TAL_TX_LO_LEAKAGE_EXTERNAL  = 0x00000200,   /*!< External Tx LO leakage calibration */
        // TAL_TX_QEC_INIT             = 0x00000400,   /*!< Tx quadrature error correction calibration */
        // TAL_LOOPBACK_RX_LO_DELAY    = 0x00000800,   /*!< Loopback Rx LO delay path calibration */
        // TAL_LOOPBACK_RX_RX_QEC_INIT = 0x00001000,   /*!< Loopback Rx quadrature error correction calibration */
        // TAL_RX_LO_DELAY             = 0x00002000,   /*!< Rx LO delay path calibration */
        // TAL_RX_QEC_INIT             = 0x00004000,   /*!< Rx quadrature error correction calibration */
        // TAL_RX_PHASE_CORRECTION     = 0x00008000,   /*!< Rx Phase correction calibration */
        // TAL_ORX_LO_DELAY            = 0x00010000,   /*!< ORx LO delay path calibration */
        // TAL_ORX_QEC_INIT            = 0x00020000,   /*!< ORx quadrature error correction calibration */
        // TAL_TX_DAC                  = 0x00040000,   /*!< Tx DAC passband calibration */
        // TAL_ADC_STITCHING           = 0x00080000,   /*!< ADC stitching calibration */
        // TAL_FHM_CALS                = 0x00800000    /*!< FHM (Fast Frequency Hopping Mode) Calibrations */

    I started with the TES GUI.  I don't have matlab so I did not use the matlab filter tool.  Is that my problem?  I should be running the Matlab tool, export the stream processor bin from that into the TES, then export the profile/config from TES?

  • Are you using the default profile available in the TES GUI to export  the talise config files?

    If not, then you need to generate the profiles from the matlab filter wizard tool, available in the below link. It will generate the profiles files. Load the profile file as it is into the TES GUI and then generate talise config files and stream files from the TES GUI for using the same into your setup.

    https://www.analog.com/en/design-center/landing-pages/001/transceiver-evaluation-software.html 

  • I have gone back and redone the configuration (profile) and stream processor using the matlab filter wizard, and then the TES gui.  

    The results are the same, any initial calibration that uses the TX aborts. 

    What should I try next?

    Below is the updated profile/configuration header after using the correct generation process.  (matlab filter wizard --> TES GUI --> c_header)

    /**
     * \file talise_config.c
     * \brief Contains Talise configuration settings for the Talise API
     *
     * Copyright 2015-2017 Analog Devices Inc.
     * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
     *
     * The top level structure taliseDevice_t talDevice uses keyword
     * extern to allow the application layer main() to have visibility
     * to these settings.
     *
     * This file may not be fully complete for the end user application and 
     * may need to updated for AGC, GPIO, and DAC full scale settings. 
     * To create a full initialisation routine, the user should also refer to the 
     * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
     *
     */
    
    #include "talise_types.h"
    #include "talise_config.h"
    #include "talise_error.h"
    #include "talise_agc.h"
    #ifdef ADI_ZYNQ_PLATFORM
    #include "zynq_platform.h"
    #endif
    
    int16_t txFirCoefs[20] = {33, -77, 123, -158, 171, -112, -155, 1040, -3011, 20121, -3011, 1040, -155, -112, 171, -158, 123, -77, 33, 0};
    
    int16_t rxFirCoefs[48] = {-7, -23, 33, 50, -70, -110, 144, 205, -259, -356, 437, 581, -698, -916, 1082, 1415, -1655, -2209, 2567, 3615, -4351, -7169, 9329, 31129, 31129, 9329, -7169, -4351, 3615, 2567, -2209, -1655, 1415, 1082, -916, -698, 581, 437, -356, -259, 205, 144, -110, -70, 50, 33, -23, -7};
    
    int16_t obsrxFirCoefs[48] = {-7, -21, 31, 48, -67, -106, 124, 164, -275, -334, 440, 552, -694, -872, 1069, 1351, -1633, -2111, 2541, 3477, -4295, -6877, 9433, 30825, 30825, 9433, -6877, -4295, 3477, 2541, -2111, -1633, 1351, 1069, -872, -694, 552, 440, -334, -275, 164, 124, -106, -67, 48, 31, -21, -7};
    
    #ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
    /*
     * Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
     * User should replace with their own structure or settings for their hardware
     */
    zynqSpiSettings_t spiDev1 =
    {
    	.chipSelectIndex = 1,
    	.writeBitPolarity = 0,
    	.longInstructionWord = 1,
    	.CPHA = 0,
    	.CPOL = 0,
    	.mode = 0,
    	.spiClkFreq_Hz = 25000000
    };
    
    /*
     * Platform Layer settings - this structure is specific to ADI's platform layer code.
     * User should replace with their own structure or settings for their hardware
     * The structure is held in taliseDevice_t below as a void pointer, allowing
     * the customer to pass any information for their specific hardware down to the
     * hardware layer code.
     */
    zynqAdiDev_t talDevHalInfo =
    {
    	.devIndex = 1,
    	.spiSettings = &spiDev1,
    	.spiErrCode = 0,
    	.timerErrCode = 0,
    	.gpioErrCode = 0,
    	.logLevel = ADIHAL_LOG_ALL
    };
    #endif
    /**
     *  TalDevice a structure used by the Talise API to hold the platform hardware
     *  structure information, as well as an internal Talise API state container
     *  (devStateInfo) of runtime information used by the API.
     **/
    taliseDevice_t talDevice =
    {
    #ifdef ADI_ZYNQ_PLATFORM
        /* Void pointer of users platform HAL settings to pass to HAL layer calls
         * Talise API does not use the devHalInfo member */
    	.devHalInfo = &talDevHalInfo,
    #else
    	.devHalInfo = NULL,     /*/** < Insert Customer Platform HAL State Container here>*/
    #endif
    	/* devStateInfo is maintained internal to the Talise API, just create the memory */
    	.devStateInfo = {0}
    
    };
    
    taliseInit_t talInit =
    {
    	/* SPI settings */
        .spiSettings =
        {
    		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
    		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
    		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
    		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
    		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
    	},
    	
        /* Rx settings */
        .rx = 
        {
            .rxProfile =
            {
                .rxFir = 
                {
                    .gain_dB = -6,                /* filter gain */
                    .numFirCoefs = 48,            /* number of coefficients in the FIR filter */
                    .coefs = &rxFirCoefs[0]
                },
                .rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
                .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
                .rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
                .rxOutputRate_kHz = 245760,            /* Rx IQ data rate in kHz */
                .rfBandwidth_Hz = 200000000,    /* The Rx RF passband bandwidth for the profile */
                .rxBbf3dBCorner_kHz = 200000,    /* Rx BBF 3dB corner in kHz */
                .rxAdcProfile = {185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
                .rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
                .rxNcoShifterCfg =
                {
                    .bandAInputBandWidth_kHz = 0,
                    .bandAInputCenterFreq_kHz = 0,
                    .bandANco1Freq_kHz = 0,
                    .bandANco2Freq_kHz = 0,
                    .bandBInputBandWidth_kHz = 0,
                    .bandBInputCenterFreq_kHz = 0,
                    .bandBNco1Freq_kHz = 0,
                    .bandBNco2Freq_kHz = 0
                }
            },
            .framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
            .rxGainCtrl = 
            {
                .gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
                .rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
                .rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
                .rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
                .rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
                .rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
                .rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
            },
            .rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
        },
    
    
        /* Tx settings */
        .tx = 
        {
            .txProfile =
            {
                .dacDiv = 1,                        /* The divider used to generate the DAC clock */
                .txFir = 
                {
                    .gain_dB = 6,                        /* filter gain */
                    .numFirCoefs = 20,                    /* number of coefficients in the FIR filter */
                    .coefs = &txFirCoefs[0]
                },
                .txFirInterpolation = 1,                    /* The Tx digital FIR filter interpolation (1,2,4) */
                .thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
                .thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
                .thb3Interpolation = 2,                    /* Tx Halfband3 filter interpolation (1,2)*/
                .txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
                .txInputRate_kHz = 245760,                    /* Primary Signal BW */
                .primarySigBandwidth_Hz = 75000000,    /* The Rx RF passband bandwidth for the profile */
                .rfBandwidth_Hz = 200000000,            /* The Tx RF passband bandwidth for the profile */
                .txDac3dBCorner_kHz = 200000,                /* The DAC filter 3dB corner in kHz */
                .txBbf3dBCorner_kHz = 100000,                /* The BBF 3dB corner in kHz */
                .loopBackAdcProfile = {243, 143, 181, 90, 1280, 485, 1275, 37, 1317, 23, 797, 35, 48, 48, 30, 174, 0, 0, 0, 0, 44, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
            },
            .deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
            .txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
            .txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
            .tx1Atten_mdB = 0,                            /* Initial Tx1 Attenuation */
            .tx2Atten_mdB = 0,                            /* Initial Tx2 Attenuation */
            .disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
        },
    
    
        /* ObsRx settings */
        .obsRx = 
        {
            .orxProfile =
            {
                .rxFir = 
                {
                    .gain_dB = -6,                /* filter gain */
                    .numFirCoefs = 48,            /* number of coefficients in the FIR filter */
                    .coefs = &obsrxFirCoefs[0]
                },
                .rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
                .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
                .rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
                .orxOutputRate_kHz = 245760,            /* Rx IQ data rate in kHz */
                .rfBandwidth_Hz = 200000000,    /* The Rx RF passband bandwidth for the profile */
                .rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
                .orxLowPassAdcProfile = {185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
                .orxBandPassAdcProfile = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
                .orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
                .orxMergeFilter  = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
            },
            .orxGainCtrl = 
            {
                .gainMode = TAL_MGC,
                .orx1GainIndex = 255,
                .orx2GainIndex = 255,
                .orx1MaxGainIndex = 255,
                .orx1MinGainIndex = 195,
                .orx2MaxGainIndex = 255,
                .orx2MinGainIndex = 195
            },
            .framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
            .obsRxChannelsEnable = TAL_ORX1ORX2,        /* The desired ObsRx Channels to enable during initialization */
            .obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
        },
    
        /* Digital Clock Settings */
        .clocks = 
        {
            .deviceClock_kHz = 122880,            /* CLKPLL and device reference clock frequency in kHz */
            .clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
            .clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
            .rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
            .rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
        },
    
        /* JESD204B settings */
        .jesd204Settings = 
        {
            /* Framer A settings */
            .framerA = 
            {
                .bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
                .M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
                .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
                .F = 4,                            /* F (number of bytes per frame) */
                .Np = 16,                            /* Np (converter sample resolution) */
                .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
                .externalSysref = 0,            /* 0=use internal SYSREF, 1= use external SYSREF */
                .serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
                .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
                .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbInSelect = 0,                /* syncbInSelect; */
                .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
                .syncbInLvdsMode = 1,
                .syncbInLvdsPnInvert = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Framer B settings */
            .framerB = 
            {
                .bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
                .M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
                .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
                .F = 4,                            /* F (number of bytes per frame) */
                .Np = 16,                            /* Np (converter sample resolution) */
                .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
                .externalSysref = 0,            /* 0=use internal SYSREF, 1= use external SYSREF */
                .serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
                .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
                .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbInSelect = 1,                /* syncbInSelect; */
                .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
                .syncbInLvdsMode = 1,
                .syncbInLvdsPnInvert = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Deframer A settings */
            .deframerA = 
            {
                .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
                .M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
                .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
                .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
                .externalSysref = 0,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
                .deserializerLanesEnabled = 0x03,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
                .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
                .lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
                .Np = 16,                /* Np (converter sample resolution) */
                .syncbOutLvdsMode = 1,
                .syncbOutLvdsPnInvert = 0,
                .syncbOutCmosSlewRate = 0,
                .syncbOutCmosDriveLevel = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            /* Deframer B settings */
            .deframerB = 
            {
                .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
                .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
                .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
                .M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
                .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
                .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
                .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
                .deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
                .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
                .lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
                .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
                .syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
                .Np = 16,                /* Np (converter sample resolution) */
                .syncbOutLvdsMode = 1,
                .syncbOutLvdsPnInvert = 0,
                .syncbOutCmosSlewRate = 0,
                .syncbOutCmosDriveLevel = 0,
                .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
            },
            .serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
            .serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
            .serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
            .desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
            .desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
            .sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
            .sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
        }
    };
    
    //Only needs to be called if user wants to setup AGC parameters
    static taliseAgcCfg_t rxAgcCtrl =
    {
        4,
        255,
        195,
        255,
        195,
        30720,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
        10,
        10,
        16,
        0,
        1,
        0,
        0,
        0,
        1,
        31,
        246,
        4,
        1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
        /* agcPower */
        {
            1,      /*!<1-bit field, enables the Rx power measurement block. */
            1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
            0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
            9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
            2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
            4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
            4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
            5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
            5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            2,      /*!<Default value should be 2*/
            0,
            0
        },
        /* agcPeak */
        {
            205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
            2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval  , Default: 4 */
            4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
            39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
            49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
            23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
            19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
            6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
            3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00  */
            4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
            2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
            1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
            1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
            1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
            181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
            45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
            3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
            2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
            4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
            8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
            4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
            1,
            0,
            0
        }
    };

  • Can you share with us the profile in python format so that we can test it on our eval board?

  • Exported python profile below. 

    Does the ARM generate any reason code or log that I can pull to help out? 

    I have not performed a dump of the arm memory, would that provide insight?

    Do you have a list of common hardware problems that would cause this?

    import clr
    import System
    import time
    clr.AddReferenceToFileAndPath("C:\\Program Files (x86)\\Analog Devices\\ADRV9009 Transceiver Evaluation Software\\AdiCmdServerClient.dll")
    from AdiCmdServerClient import AdiCommandServerClient
    from AdiCmdServerClient import Talise
    from AdiCmdServerClient import FpgaTalise
    from AdiCmdServerClient import FpgaTddGpioConfig
    from AdiCmdServerClient import TaliseArmGpioConfig
    from AdiCmdServerClient import DacSampleXbar
    from AdiCmdServerClient import TaliseRxDataFormat
    from AdiCmdServerClient import GpioSel
    from System import Array
    
    #Create an Instance of the Class
    Link = AdiCommandServerClient.Instance
    #Connect to the Zynq Platform
    if(Link.hw.Connected == 1):
    	Connect = 0
    else:
    	Connect = 1
    	Link.hw.Connect("192.168.1.10", 55555)
    #Read the Version
    print Link.Version()
    
    ##################################################
    # # GUI Version: 3.6.2.1		DLL Version: 3.6.2.1	FPGA Version: No Connection	ArmVersion: 0.0.0 Build type = TAL_ARM_BUILD_DEBUG	StreamVersion: 2.17
    ##################################################
    Link.FpgaTalise.StopTxData()
    Link.SetSpiChannel(1)
    Link.FpgaTalise.ResetFpgaRegisters()
    Link.FpgaTalise.ResetFpgaIp(FpgaTalise.FpgaResets.ClearAllRst)
    
    ##################################################
    # Init Structures
    ##################################################
    Link.Talise.InitClearProfiles()
    Link.Talise.InitClocks(1, 122880, 9830400, 2, Talise.HsDiv.HsDiv2p5)
    Link.Talise.InitRfPllUseExternalLo(1, 0)
    Link.Talise.InitRxProfiles(1, 2, 4, 1, 245760, 200000000, 200000, Array[System.Int16]([185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905]),Talise.RxDdcMode.RxDdcBypass)
    Link.Talise.InitFirFilters(1, Talise.FilterName.Rx, "C:\\Users\\David\\AppData\\Local\\Temp\\RX_FIR.txt")
    Link.Talise.InitRxSettings(1, Talise.RxChannel.Rx1Rx2, Talise.FramerSelect.FramerA)
    Link.Talise.InitTxProfiles(1, 1, 1, 2, 2, 2, 1, 245760, 75000000, 200000000, 200000, 100000, Array[System.Int16]([243, 143, 181, 90, 1280, 485, 1275, 37, 1317, 23, 797, 35, 48, 48, 30, 174, 0, 0, 0, 0, 44, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905]))
    Link.Talise.InitFirFilters(1, Talise.FilterName.Tx, "C:\\Users\\David\\AppData\\Local\\Temp\\TX_FIR.txt")
    Link.Talise.InitTxSettings(1, Talise.TxAttenStepSize.TxAtten0P05DB, Talise.TxChannel.Tx1Tx2, 0, 0, Talise.DeframerSelect.DeframerA, Talise.TxDataIfPllUnlock.TxRampedDownToZero)
    Link.Talise.InitObsProfiles(1, 2, 4, 1, 245760, 200000000, 225000, Array[System.Int16]([185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905]),Array[System.Int16]([0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]),Talise.OrxDdcMode.OrxDdcDisabled, Array[System.Int16]([0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]))
    Link.Talise.InitFirFilters(1, Talise.FilterName.ORx, "C:\\Users\\David\\AppData\\Local\\Temp\\ORX_FIR.txt")
    Link.Talise.InitObsRxSettings(1, Talise.ObsRxChannel.ObsRx1Rx2, Talise.ObsRxLoSource.RfPll, Talise.FramerSelect.FramerB)
    Link.Talise.InitRfPllEnablePhaseSync(1, Talise.RfPllMcs.NoSync)
    Link.Talise.InitRxNcoShiftCfg(1, 0, 0, 0, 0, 0, 0, 0, 0)
    
    ##################################################
    # Init Jesd
    ##################################################
    Link.Talise.InitJesd204bFramer(1, Talise.FramerSelect.FramerA, 1, 0, 0, 4, 32, 4, 16, 1, 0, 3, 228, 31, 0, 0, 0, 1, 0, 0)
    Link.Talise.InitJesd204bFramer(1, Talise.FramerSelect.FramerB, 0, 0, 0, 4, 32, 4, 16, 1, 0, 12, 228, 31, 0, 1, 0, 1, 0, 0)
    Link.FpgaTalise.SetupTxConvXbar(FpgaTalise.FpgaFramerSelect.FramerA, 0xE4)
    Link.FpgaTalise.SetupTxConvXbar(FpgaTalise.FpgaFramerSelect.FramerB, 0xE4)
    Link.GetPcbDescript()
    Link.Talise.InitJesd204bDeframer(1, Talise.DeframerSelect.DeframerA, 0, 0, 0, 4, 32, 1, 0, 3, 228, 17, 0, 0, 16, 1, 0, 0, 0, 0)
    Link.FpgaTalise.ResetFpgaIp(FpgaTalise.FpgaResets.TxJesdRst)
    time.sleep(0.5)
    Link.FpgaTalise.ResetFpgaIp(FpgaTalise.FpgaResets.ClearAllRst)
    Link.FpgaTalise.SetupJesd204(122880, 245760, 4, 3, 32, 1, 1, 16, 245760, 4, 3, 32, 1, 16, 245760, 4, 12, 32, 1, 1, 16, FpgaTalise.FpgaFramerSelect.FramerA, FpgaTalise.FpgaDeframerSelect.DeframerA, FpgaTalise.FpgaDeframerSelect.DeframerB, False)
    
    ##################################################
    # Program Talise
    ##################################################
    Link.Talise.ResetDevice()
    Link.Talise.Initialize()
    Link.Talise.SetDacFullScale(Talise.DacFullScale.DacFs0dB)
    pllStatus = Link.Talise.GetPllsLockStatus()
    print 'Talise pllStatus =', hex(pllStatus)
    Link.Talise.EnableMultichipSync(0x1, 0x0)
    Link.FpgaTalise.RequestSysref()
    Link.FpgaTalise.RequestSysref()
    Link.FpgaTalise.RequestSysref()
    time.sleep(0.1)
    mcsStatus = Link.Talise.EnableMultichipSync(0x0, 0x0)
    print 'MCS Status = ', hex(mcsStatus)
    
    Link.FpgaTalise.SetupJesd204bOversampler(FpgaTalise.FpgaDeframerSelect.DeframerB, FpgaTalise.FpgaSampleDecimation.DecimateBy1)
    Link.SetLogLevel(0)
    if pllStatus & 0x01:
    	Link.Talise.InitArm()
    	Link.Talise.LoadStreamProcessor("C:\\Users\\David\\AppData\\Local\\Temp\\TaliseStream.bin")
    	Link.Talise.LoadArm("C:\\Program Files (x86)\\Analog Devices\\ADRV9009 Transceiver Evaluation Software\\Resources\\arm_firmware\\TaliseTDDArmFirmware.bin")
    	isArmGood = Link.Talise.VerifyArmChecksum()
    	print 'isArmGood =', hex(isArmGood)
    	if isArmGood & 1:
    		print "ARM Loaded Successfully"
    	else:
    		print "ARM File not loaded correctly"
    else:
    	print "pll Lock Status is Incorrect"
    Link.Talise.GetArmVersion()
    Link.SetLogLevel(63)
    Link.Talise.SetPllLoopFilter(Talise.PllName.RfPll, 50, 3)
    Link.Talise.SetRfPllFrequency(Talise.PllName.RfPll, 2000000000)
    pllStatus = Link.Talise.GetPllsLockStatus()
    print 'Talise pllStatus =', hex(pllStatus)
    
    ##################################################
    # InitCals
    ##################################################
    Link.Talise.AbortInitCals(0)
    #initCalMask = 0
    #initCalMask |= int(Link.Talise.CalMask.TxBaseBandFilter)
    #initCalMask |= int(Link.Talise.CalMask.AdcTuner)
    #initCalMask |= int(Link.Talise.CalMask.Tia3dBCorner)
    #initCalMask |= int(Link.Talise.CalMask.DcOffset)
    #initCalMask |= int(Link.Talise.CalMask.RxGainDelay)
    #initCalMask |= int(Link.Talise.CalMask.FlashCal)
    #initCalMask |= int(Link.Talise.CalMask.PathDelay)
    #initCalMask |= int(Link.Talise.CalMask.TxLoLeakageInternal)
    #initCalMask |= int(Link.Talise.CalMask.TxQecInit)
    #initCalMask |= int(Link.Talise.CalMask.LoopbackRxLoDelay)
    #initCalMask |= int(Link.Talise.CalMask.LoopbackRxRxQecInit)
    #initCalMask |= int(Link.Talise.CalMask.RxQecInit)
    #initCalMask |= int(Link.Talise.CalMask.ORxQecInit)
    #initCalMask |= int(Link.Talise.CalMask.TxDac)
    Link.Talise.RunInitCals(0x65DEF)
    Link.Talise.WaitInitCals(60000, 0)
    
    ##################################################
    # Framer/Deframer
    ##################################################
    Link.FpgaTalise.EnableJesd204bFramer(FpgaTalise.FpgaFramerSelect.DisableAll)
    Link.FpgaTalise.ResetFpgaIp(FpgaTalise.FpgaResets.TxJesdRst)
    Link.FpgaTalise.ResetFpgaIp(FpgaTalise.FpgaResets.ClearAllRst)
    Link.FpgaTalise.EnableJesd204bFramer(FpgaTalise.FpgaFramerSelect.FramerA)
    Link.Talise.EnableDeframerLink(Talise.DeframerSelect.DeframerA, 0)
    Link.Talise.EnableDeframerLink(Talise.DeframerSelect.DeframerA, 1)
    Link.Talise.EnableSysrefToDeframer(Talise.DeframerSelect.DeframerA, 1)
    Link.FpgaTalise.EnableJesd204bDeframer(FpgaTalise.FpgaDeframerSelect.DisableAll)
    Link.Talise.EnableFramerTestData(Talise.FramerSelect.FramerA, Talise.FramerDataSource.FtdAdcData, Talise.FramerInjectPoint.FtdFramerInput)
    Link.Talise.EnableFramerTestData(Talise.FramerSelect.FramerB, Talise.FramerDataSource.FtdAdcData, Talise.FramerInjectPoint.FtdFramerInput)
    Link.FpgaTalise.ResetFpgaIp(FpgaTalise.FpgaResets.ClearAllRst)
    Link.FpgaTalise.ResetFpgaIp(FpgaTalise.FpgaResets.RxJesdRst)
    Link.FpgaTalise.ResetFpgaIp(FpgaTalise.FpgaResets.ClearAllRst)
    Link.FpgaTalise.EnableJesd204bDeframer(FpgaTalise.FpgaDeframerSelect.DeframerAandB)
    Link.Talise.EnableFramerLink(Talise.FramerSelect.FramerAandB, 0)
    Link.Talise.EnableFramerLink(Talise.FramerSelect.FramerAandB, 1)
    Link.Talise.EnableSysrefToFramer(Talise.FramerSelect.FramerAandB, 1)
    Link.FpgaTalise.RequestSysref()
    Link.Talise.ReadFramerStatus(Talise.FramerSelect.FramerA)
    Link.Talise.ReadFramerStatus(Talise.FramerSelect.FramerB)
    Link.Talise.ReadDeframerStatus(Talise.DeframerSelect.DeframerA)
    
    ##################################################
    # Tracking Cals
    ##################################################
    time.sleep(1)
    #trackingCalMask = 0
    Link.Talise.EnableTrackingCals(0)
    
    ##################################################
    # GainWithFloatingPoint or GainWithNoCompensation
    ##################################################
    #Ensure Stream File has been set to receive Floating Point Data
    rxDataFormatter = TaliseRxDataFormat()
    rxDataFormatter.FormatSelect = (rxDataFormatter.FormatSelect.GainCompensationDisabled)
    rxDataFormatter.FpNumExpBits = (rxDataFormatter.FpNumExpBits.TwoExponentBits)
    rxDataFormatter.FpRoundMode = (rxDataFormatter.FpRoundMode.RoundToEven)
    rxDataFormatter.FpRx1Atten = (rxDataFormatter.FpRx1Atten.FpAtten0dB)
    rxDataFormatter.FpRx2Atten = (rxDataFormatter.FpRx2Atten.FpAtten0dB)
    rxDataFormatter.FpHideLeadingOne = (1)
    rxDataFormatter.IntEmbeddedBits = (rxDataFormatter.IntEmbeddedBits.Embed1SlicerBitAtLsb)
    rxDataFormatter.IntSampleResolution = (rxDataFormatter.IntSampleRes.Integer12Bit2sComp)
    Link.Talise.SetRxDataFormat(rxDataFormatter)
    #Link.Talise.SetRxDataFormat(TaliseRxDataFormat.0,0,0,0,0,1,0,0,2,0,0,3,3,0,0)
    
    ##################################################
    # Set Gain & Attenuation
    ##################################################
    Link.Talise.SetRxManualGain(Talise.RxChannel.Rx1, 255)
    Link.Talise.SetRxManualGain(Talise.RxChannel.Rx2, 255)
    Link.Talise.SetObsRxManualGain(Talise.ObsRxChannel.ObsRx1, 255)
    Link.Talise.SetObsRxManualGain(Talise.ObsRxChannel.ObsRx2, 255)
    Link.Talise.SetTxAttenuation(Talise.TxChannel.Tx1, 0)
    Link.Talise.SetTxAttenuation(Talise.TxChannel.Tx2, 0)
    
    ##################################################
    # Disconnect from the Zynq
    ##################################################
    if(Connect == 1):
    	Link.hw.Disconnect()
    

  • Can you send us the filter files(RX,TX and ORX) that you are loading into python script ? Or can you send us a snippet of the filter wizard tool with information on the sampling rates and BW's used so that we can generate the same profile and try it on our end.

     I tried with default filter files and was able to run the script with TX related init cals without any issue

    Looks like a configuration issue. 

  • I did not load any special filters, I am running defaults.  My intention was to get this up and running with the default and then focus on details such as the filters.  For my use case the rx and tx bandwidths should match. 

    Here is a screen shot of my setting for the Matlab tool.

    Below is the main output file from the matlab profile configuration wizard.

    <profile Talise version=1 name=Tx_BW200_IR245p76_Rx_BW200_OR245p76_ORx_BW200_OR245p76>
     <clocks>
      <deviceClock_kHz=122880>
      <clkPllVcoFreq_kHz=9830400>
      <clkPllHsDiv=2.5>
     </clocks>
    
     <rx name=Rx 200.00MHz, OutputRate 245.76MHz, TotalDecimation 8>
      <rxChannels=TAL_RX1RX2>
      <rxFirDecimation=2>
      <rxDec5Decimation=4>
      <rhb1Decimation=1>
      <rxOutputRate_kHz=245760>
      <rfBandwidth_Hz=200000000>
      <rxBbf3dBCorner_kHz=200000>
      <rxDdcMode=0>
    
      <rxNcoShifterCfg>
       <bandAInputBandWidth_kHz=0>
       <bandAInputCenterFreq_kHz=0>
       <bandANco1Freq_kHz=0>
       <bandANco2Freq_kHz=0>
       <bandBInputBandWidth_kHz=0>
       <bandBInputCenterFreq_kHz=0>
       <bandBNco1Freq_kHz=0>
       <bandBNco2Freq_kHz=0>
      </rxNcoShifterCfg>
    
      <filter FIR gain_dB=-6 numFirCoefs=48>
      -7
      -23
      33
      50
      -70
      -110
      144
      205
      -259
      -356
      437
      581
      -698
      -916
      1082
      1415
      -1655
      -2209
      2567
      3615
      -4351
      -7169
      9329
      31129
      31129
      9329
      -7169
      -4351
      3615
      2567
      -2209
      -1655
      1415
      1082
      -916
      -698
      581
      437
      -356
      -259
      205
      144
      -110
      -70
      50
      33
      -23
      -7
      </filter>
    
      <rxAdcProfile num=42>
      185
      141
      172
      90
      1280
      942
      1332
      90
      1368
      46
      1016
      19
      48
      48
      37
      208
      0
      0
      0
      0
      52
      0
      7
      6
      42
      0
      7
      6
      42
      0
      25
      27
      0
      0
      25
      27
      0
      0
      165
      44
      31
      905
      </rxAdcProfile>
     </rx>
    
     <obsRx name=Rx 200.00MHz, OutputRate 245.76MHz, TotalDecimation 8>
      <obsRxChannelsEnable=TAL_ORX1ORX2>
      <enAdcStitching=0>
      <rxFirDecimation=2>
      <rxDec5Decimation=4>
      <rhb1Decimation=1>
      <orxOutputRate_kHz=245760>
      <rfBandwidth_Hz=200000000>
      <rxBbf3dBCorner_kHz=225000>
      <orxDdcMode=0>
    
      <filter FIR gain_dB=-6 numFirCoefs=48>
      -7
      -21
      31
      48
      -67
      -106
      124
      164
      -275
      -334
      440
      552
      -694
      -872
      1069
      1351
      -1633
      -2111
      2541
      3477
      -4295
      -6877
      9433
      30825
      30825
      9433
      -6877
      -4295
      3477
      2541
      -2111
      -1633
      1351
      1069
      -872
      -694
      552
      440
      -334
      -275
      164
      124
      -106
      -67
      48
      31
      -21
      -7
      </filter>
    
      <orxLowPassAdcProfile num=42>
      185
      141
      172
      90
      1280
      942
      1332
      90
      1368
      46
      1016
      19
      48
      48
      37
      208
      0
      0
      0
      0
      52
      0
      7
      6
      42
      0
      7
      6
      42
      0
      25
      27
      0
      0
      25
      27
      0
      0
      165
      44
      31
      905
      </orxLowPassAdcProfile>
    
      <orxBandPassAdcProfile num=42>
      185
      141
      172
      90
      1280
      942
      1332
      90
      1368
      46
      1016
      19
      48
      48
      37
      208
      0
      0
      0
      0
      52
      0
      7
      6
      42
      0
      7
      6
      42
      0
      25
      27
      0
      0
      25
      27
      0
      0
      165
      44
      31
      905
      </orxBandPassAdcProfile>
    
     </obsRx>
    
     <lpbk>
      <rxFirDecimation=2>
      <rhb1Decimation=1>
      <outputRate_kHz=245760>
      <rfBandwidth_Hz=75000000>
      <rxBbf3dBCorner_kHz=225000>
    
      <filter FIR gain_dB=-6 num=48>
      -7
      -21
      31
      48
      -67
      -106
      124
      164
      -275
      -334
      440
      552
      -694
      -872
      1069
      1351
      -1633
      -2111
      2541
      3477
      -4295
      -6877
      9433
      30825
      30825
      9433
      -6877
      -4295
      3477
      2541
      -2111
      -1633
      1351
      1069
      -872
      -694
      552
      440
      -334
      -275
      164
      124
      -106
      -67
      48
      31
      -21
      -7
      </filter>
    
      <lpbkAdcProfile num=42>
      243
      143
      181
      90
      1280
      485
      1275
      37
      1317
      23
      797
      35
      48
      48
      30
      174
      0
      0
      0
      0
      44
      0
      7
      6
      42
      0
      7
      6
      42
      0
      25
      27
      0
      0
      25
      27
      0
      0
      165
      44
      31
      905
      </lpbkAdcProfile>
     </lpbk>
    
     <tx name=Tx 200.00MHz, InputRate 245.76MHz, TotalInterpolation 8>
      <txChannels=TAL_TX1TX2>
      <dacDiv=1>
      <txFirInterpolation=1>
      <thb1Interpolation=2>
      <thb2Interpolation=2>
      <thb3Interpolation=2>
      <txInt5Interpolation=1>
      <txInputRate_kHz=245760>
      <primarySigBandwidth_Hz=75000000>
      <rfBandwidth_Hz=200000000>
      <txDac3dBCorner_kHz=200000>
      <txBbf3dBCorner_kHz=100000>
    
      <filter FIR gain_dB=6 numFirCoefs=20>
      33
      -77
      123
      -158
      171
      -112
      -155
      1040
      -3011
      20121
      -3011
      1040
      -155
      -112
      171
      -158
      123
      -77
      33
      0
      </filter>
     </tx>
    </profile>

  • I have tried several different bandwidth configurations.  Including not changing any settings, except to select a 122.88MHz clock.  That way I have as close to a default configuration as possible.   All configurations I try produce the arm abort on init cal.

    Alternative path/idea.  Can you provide me with a known good configuration structure (.c) along with the arm firmware.bin and stream processor.bin files?   That would let me run something that is known to work.  If that fails we know this is something other then the configuration.  If it works, then we can start to isolate the difference.

    What do you think?

  • Please download the latest GUI and package and Check whether your facing the same  error .

    https://www.analog.com/en/design-center/landing-pages/001/transceiver-evaluation-software.html

    As the Init cals are failing please check the power supply if it is clean and jitter free and is isolated from other power supplies. Make sure that the Decaps are inserted to filter the high frequency noise coming from the power supply.