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ADRV9009 framerstatus 0x27, continous sysref

Category: Software
Product Number: ADRV9009


I'm working in on a custom board with ADRV9009, and continuous SYSREF from FPGA.

Sometime, FramerStatus is 0x27. SYNC pin is always 1. I haven't seen anything special at RX data from ADRV9009 to FPGA.

According to user guide, Bit 1: SYSREF phase error, a new SYSREF had different timing than the first that set the LMFC timing. In continuous SYSREF mode, does this bit make any sense, and what is the first SYSREF that set the LMFC timing?

Best regards.

  • What is the SYSREF frequency that you are using? For continuous SYSREF, keep the  Sysref frequency less than sampleRate/64  as it is  required to meet the wait period.

    The first SYSREF pulse resets the device clock divider, which causes the clock phase-locked loop (PLL) to relock. There is a required wait period before any further SYSREF pulses are registered. The wait period is set to 1,024 phase frequency detector (PFD) reference clock periods.

     From user guide ,

    When multichip sync is enabled, the function is performed in four stages; each one is initiated with a rising SYSREF edge. The first two SYSREF rising edges synchronize the device clock dividers. This portion of the synchronization requires some amount of time for the clock PLL outputs to settle. The third SYSREF rising edge synchronizes the high speed digital clock dividers. The fourth SYSREF rising edge synchronizes the numerically controlled oscillators (NCOs), the JESD204B LMFC, and the RF PLL phase synchronization.

  • Sysref frequency is 2MHz, Refclock is 256MHz, PFD frequency is 64MHz.

    In the first configuration (power on),  FramerStatus is 0x25. Later, sometime FramerStatus is 0x27.

    "The fourth SYSREF rising edge synchronizes the JESD204B LMFC" - In continuous sysref mode, is LMFC resynchronizes?

  • What is the sampling rate frequency(the input rate to the FIR, or the rate at which the FIR runs) that you are using? The SYSREF frequency should be less than sampling rate/64