Hi,
We have a custom design using the ADRV9009 and are encountering issues with sample rates of 40Msps or 80Msps. We can generate profiles (attached) without error but they cannot be imported. TALISE_initDigitalClocks fails with the error: "Unsupported PLL reference clock or refclk out of range"
Note: Our design can select between different VCXOs and in the case described it is configured for 100MHz.
Can you confirm these rates are achievable and that the attached profile settings are correct?
Looking closer at the implementation [1],[2], TALISE_initDigitalClocks() wont accept a deviceClock_kHz of 80000. In this case, scaledRefClk_kHz is computed to 80000 and that exceeds the bounds for the final if/then/else statement which calculates the vcoCalOffset, loopFilterIcp, loopFilterC2C1, loopFilterR1C3, loopFilterR3 and the function exits.
Thank you for your support, and we appreciate any suggestions or workarounds you can provide.