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Error : 680718: RFPLL Synth Lock failed ; error: TALISE_setRfPllFrequency() failed

Hii,

I’m using ADRV9009_ZC706 basic driver. While programming the FPGA we are getting the “TALISE_setRfPllFrequency() failed”. Here I’m attaching the log file what exactly we are getting:

I’m get stuck at this point ( setRfpllFrequency failed). Help us to slove this issue.

warning: TALISE_enableMultichipSync() failed

talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5

ERROR: 294: TALISE_waitArmCmdStatus() failed due to thrown ARM error. Is device in correct state for calling command?

  • Sorry for the delay in response. Are you still facing the issue?

    Are you using eval board or custom board?

    What is the DEV_CLK frequency that you are supplying to the chip? Can you  probe and check the sysref frequency which is going at sysref input to the chip? Make sure that it is within the datasheet specs:

    Also check if the setup and the hold times are met with respect to the datasheet specs:

  • Hi Sir,

         The issues is not yet solved. Actually we are using the custom board in that the clock is hmc7044. Here actually we are using for 100MHz bandwidth so, we set DEV_CLK to 122.88MHz.The SYS_REF CLK is coming and it is observed in ILA

  • Can you send us your full init sequence? Are you using the default settings? Are you loading any custom profile generated by the filter wizard tool? For setting the RFPLL frequency, the device should be in radio off state. Refer to the "RFPLL frequency change procedure" section in UG.