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How to realize that the phase difference of the receiving channel between two adrv9009 is fixed after powerid on?

One hmc7044 is connected to two adrv9009. At present, FPGA has correctly sample the RX data of two adrv9009. we found that the phase difference between Rx channels of two adrv9009 will change after the power is powered on again. How to realize that the phase difference of the receiving channels of the two adrv9009 does not change after the power supply is powered on again?

  • You need to enable the MCS and the RFPLL phase sync capability of ADRV9009. Refer to the "RF PLL PHASE SYNCHRONIZATION" section in UG. Enabling both the features will give constant phase difference between both the boards across multiple boot ups.

  • my code is from the reference code of ADI. The synchronization function is executed in the code. The IP core of jesd204b is Xilinx.

  • for (t = TALISE_A; t < 2; t++)
    {
    if(t==0)
    {
    talInit.jesd204Settings.framerA.serializerLanesEnabled=0x0f;//serInvertLanePolarity
    //talInit.jesd204Settings.serInvertLanePolarity=1<<1;
    }
    else
    {
    talInit.jesd204Settings.framerA.serializerLanesEnabled=0x0f;//serInvertLanePolarity
    //talInit.jesd204Settings.serInvertLanePolarity=(3<<1)|(2<<1)|(1<<1);
    }
    bat_multi_spi_set(t+1);
    my_mdelay(1);
    err = talise_setup(&tal[t], &talInit,t);
    if (err != ADIHAL_OK)
    printf("Bye\n");//goto error_3;
    bat_jesd204b_ip_reset(t+1);
    }
    mdelay(10);
    //#if defined(ZU11EG) || defined(FMCOMMS8_ZCU102)
    //printf("Performing multi-chip synchronization...\n");
    for(int i=0; i < 12; i++)
    {
    //for (t = TALISE_A; t < TALISE_DEVICE_ID_MAX; t++)
    for (t = TALISE_A; t < 2; t++)
    {
    bat_multi_spi_set(t+1);
    my_mdelay(10);
    err = talise_multi_chip_sync(&tal[t], i);
    if (err != ADIHAL_OK)
    printf("Bye\n");//goto error_3;
    }
    }
    //#endif
    ADIHAL_sysrefReq(tal[TALISE_A].devHalInfo, SYSREF_CONT_ON);

  • Are you setting the "TAL_RFPLLMCS_INIT_AND_CONTTRACK" in the taliseRfPllMcs_t structure before programming the chip? You need to enable both the MCS as well as the RFPLL MCS to achieve phase synchronisation

    Refer to the "Enabling the LO Phase Sync Function Using the API " section in UG for details.