Hello. I am using the hdl 'master' branch . And i am using no-os master branch. And I am using the project design for zc706 and EVAL-ADRV9008/9.
I have migrate the reference design into our custom board. I found that the tx_jesd status always stuck at CGS while debugging first time after power on because the SYSREF isn't captured. I paste the jesd status below:
I found that this line write 0x91 to reg 0x403 and 0x00 to reg 0x402,it means that set the SPI SYSREF request into '1',and it works.But I use the ad9528_spi_read_n API to read the reg 0x403 and 0x402 after this line , the value become 0x90 and 0x00, the SPI SYSREF request reg turn itself from '1' to '0'. I can't find anywhere the spi change the value , can you help me? Any reply would be helpful.Thanks.