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QEC issue when bypassing ad9528 PLL1

Hi,

I'm having an issue with the adrv9008-1/W-PCBZ and adrv9008-2/W-PCBZ when bypassing ad9528 PLL1.

My setup is composed from a zcu102 board, connected to adrv9008-2/W-PCBZ on HPC0 and adrv9008-1/W-PCBZ on HPC1. Tx1 is connected to Rx1 via an SMA cable and the same for Tx2 and Rx2.

firmware : No-OS_2019_R2
hdl : hdl_2019_R2.
vivado 2019.1
XilinxSDK 2019.1

I did some slight changes to be able to use HPC0 and HPC1 simultaneously.

The code continuously transmits a sine wave via adrv9008-2/W-PCBZ Tx1 and Tx2, and receives it via adrv9008-1/W-PCBZ Rx1 and Rx2 after passing through SMA cables. The digital received signal is then exported via xilinx ILA.

Configuration 1 : using ad9528 PLL1 (both ad9528 chips are provided with the same external 30.72 MHz), the received signal is perfect.

(600 samples and 6000 samples)


Configuration 2 : when bypassing PLL1 (forcing holdover with the VCXO 122.88 MHz, so the external 30.72 MHz is not used) the received signal presents imperfections.

(1000 samples and 6000 samples)

In this latter case, LOs (of adrv9008-2/W-PCBZ and adrv9008-1/W-PCBZ) present and offset of around 10 kHz between each others, which implies that their input reference clocks are not synchronous (which is the case), but 10 kHz is still a reasonable value and does not explain this imperfection.

I prepared a second setup with different ZCU102 and adrv boards, but always getting the same results.

My main issue is that when integrating my proprietary PHY, The SNR falls from 37 dB (in config1) to 20 dB (in config2).

Any help please ?