I would like to find out if it is possible to control the ADRV9009 JESD204B serializer / transmitter amplitude (peak to peak). I believe I can control the FPGA serializer / transmitter amplitude using the adi,jesd204-ser-amplitude device tree entry. However, I can't seem to find anything indicating whether the ADRV9009 JESD204B serializer/ transmitter amplitude can be controlled.
The reason I am asking:
My JESD204B lanes (both transmit and receive) operate at 8.32Gbps. Depending on my IF frequency, I am seeing a spur in the output spectrum related to the JESD204B lane rate. So for example, when I tune the ADRV9009 LO to 932MHz, the 9th harmonic of this LO frequency is 8388000000. There is a strong spur at 68MHz corresponding to the 8.32GHz of the JESD204B high speed serial lanes.
Another example, when I tune the ADRV9009 LO to 1842MHz, the 9th harmonic of this LO frequency is 16578000000. There is a strong spur at 62MHz corresponding to the 2nd harmonic of the 8.32GHz of the JESD204B high speed serial lanes.
The lane length between the ADRV9009 and the FPGA are short (< 100mm) so it is OK for me to reduce the transmitter amplitude and still get reliable link up. I have improved the spur level by a couple of dBs by setting the FPGA transmitter amplitude level to minimum. I am still getting a reliable JESD204B link. I would now like to do the same to the ADRV9009 JESD204B transmitter amplitude level.