ADRV9009-W/PCBZ + Zcu102 Custom TX chain without PS core, only logic


Working with only PL side, im trying to setup a TX chain with custom DATA feeding TPL via util_upack module.

My goal is to have a working JESD link and observe my data from TX using a scope.

I managed to configure JESD register map manually via custom AXI module. I am now wondering how to configure ADRV9009 and AD9528 clock module (using SPI ?).

Without any configuration for ADRV9009 JESD link is stuck in CGS state. I disabled SYSREF handling to simplify. I suspect a clock issue due to lack of configuration for ADRV device.

With ILA i spied tx_out_clock signal from XCVR module, and the clock is running. But tx_sync signal is always 0. Whats the issue here ?