I am looking for advice on something we have been observing on a lab bench over the past few days.
The test setup is an ADRV9009 ZU11EG SOM with fmcomms8 and carrier card (4xADRV9009, 8 channels, 2 chips per board). A constant tone at 5795 MHz from a signal generator is passed through an 8-way splitter, then received on all channels. Multiple data captures are repeated every 5 seconds, and relative phase with respect to a reference channel is measured on each. The relative phase of each channel is plotted with the mean of each channel removed, to emphasize any differences from steady state behavior.
Question #1 – Slowly Varying Board to Board Relative Phase
After starting the system, letting the JESD-FSM sync, and making measurements for several minutes, relative phase plots board_to_board_phase<1-3>.png were formed. From power-on, there exists a board-to-board phase delta that seems to slowly vary on the order of several minutes. In this case the normalizing channel was a DB channel, so the DB appears constant, and the SOM channels change relative to it. Had a SOM channel been chosen as a reference, the opposite would occur.
Is this expected? Are there configuration items that can adjusted to reduce this board-to-board drift?
In terms of root cause, would you suspect clock drift between the HMC7044s on the SOM vs. daughtercard, the temperature loop depicted in UG1295 pg 114 Figure 64, or something else?
The absolute value of each channel-to-channel phase measurement is not important to us; in this setup the cables are not phase matched, and the splitter delays are not compensated for. What we are interested in is minimizing the time varying behavior, as it translates to an error in downstream signal processing.
Question #2 – Rapidly Varying Board to Board Relative Phase
Taking this one step further, once the system has warmed up, a bench fan was applied to the daughterboard for a few minutes, then removed. A large, rapid jump in board-to-board phase can be observed in the board_to_board_phase_with_fan1.png plot.
Is this expected? This is a dramatic change in phase… is this oscillator instability of the local VCXO external references used by the HMC7044s on the SOM and DB? Temperature vs. time, as in UG1295 Table 46 and Figure 74? Something else?
Appreciate the help. Just trying to understand things a bit more thoroughly as we work through our design, making sure we understand which effects need to be compensated for, and what kind of cooling strategies to avoid with these chipsets.