ADRV9009. FPGA's DDS generated CW results in Tx harmonics (picket fence)

Is there an ADRV9009 configuration that I need to apply to remove Tx harmonics?

Using TALISE_enableTxNco with LO set to 1.8 Ghz, I am able to configure frequencies and see a single Tx spectra for each of the following TxNco frequency settings: 10, 60, or 80 Mhz.

However, when I setup FPGA to generate/Tx a 12.8 Mhz CW, using Xilinx DDS Compiler 6.0 through to JESDB and then to ADRV9009, I am seeing harmonics (picket fence) at the ADRV9009 Tx1 port..

Sampling rate is 204.8, thus from ILA's 16 cycles results in 12.8 Mhz (verifies the correct frequency inside FPGA and it looks clean)

Clarifying TALISE_enableTxNco experimentation
[edited by: luis at 10:46 PM (GMT -5) on 13 Jan 2021]