MGT REF CLOCK CONNECTION FOR DAC,ADC

Hi ADI-Team,

We are designing a board using Xilinx MPSoC,ADRV9008-1 and ADRV9008-2.

We should be able to configure DAC and ADC independently with different sampling rates.REF_CLK for DAC(ADRV9008-2) and ADC(ADRV9008-1) is being generated by a JESD Clock Generator.
Query:
We have connected JESD Data and Clock lines for both DAC and ADC in same bank(Bank 230).


We have Bank 229 available.Just need a suggestion which approach will be better,connecting Bank 229 and Bank 230 separately for DAC and ADC or both DAC and ADC in same Bank.

Thanks

  • 0
    •  Analog Employees 
    on Jan 13, 2021 9:24 AM 1 month ago

    Hello,

    We are using the same banks for RX/TX/ORx on our ADRV9009 projects. It's important to have the same clock source for the ADRV9008-x and FPGA.

    The only advantage you would have in using different banks for ADC / DAC is that you could use the QPLL for both paths, but for the MPSOCs we used the CPLL maximum frequency is 12.5 Gbps, so CPLL covers the requirement of the ADRV900x device.

    In our designs, when possible, we try to provide additional clocks for data link layer (through an PL global clock pin) and not derive it through an MMCM as we do on the ADRV9009 reference design. Please see clocking tree diagram at https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg/hardware

    Regards,

    Adrian

  • Thank you so much for  prompt response.

    We are using same clock source(AD9528) for ADRV9008-x and FPGA.

    Also thanks for information to provide additional clocks for data link layer.This i think corresponds to core clock(JESD204B SUBCLASS 1) generated from HMC7044 in ADRV9009-ZU11EG evaluation board schematics.We are generating core clock for ADC and DAC from AD9528.

    Query with reference to MGT bank connection:

    We will be operating in FDD mode where ADC and DAC must be programmed for different sampling frequencies simultaneously. Please suggest whether to connect to two different banks or same bank.

    Regards

    Siddharth

  • 0
    •  Analog Employees 
    on Jan 14, 2021 9:24 AM 1 month ago in reply to Sid@123

    Hello Siddharth,

    What are the frequencies you have in mind ? What lane rates ?

    Regards,

    Adrian

  • Hi Adrian,

    We are planning to use full capability of ADC and DAC

    TX Sampling Rate up to 500 MSPS and RX Sampling rate up to 370 MSPS.

    And Lane rate that we will be targeting is: 3.125-3.6G.(L=4,M=2,N=16 for our case as we will be operating in 1RX-1TX mode)

    I have some doubts with respect to lane rate calculation "Min lane rate supported is 3.125G but in ADRV9009-TES,its showing 2.4576G for one of the setting". Which one is correct?

    Thanks

  • 0
    •  Analog Employees 
    on Jan 19, 2021 3:21 PM 1 month ago in reply to Sid@123

    Hello,

    For ADRV9008-2 you don't plan to use the Observation path ? 

    Regarding the Min lane rate support, I will move this question to the appropriate forum. Also, to my knowledge the maximum bandwidth on the RX side of ADRV9008-1 is 200MHz and I'm not sure RX can be used at 370MSPS.

    Regards,

    Adrian