i am using ADRV9009 with our own FPGA board for TDD. I want to get the exact RF PLL lock time when changing the RF freq (RF hop is not suitable in this case).
and I totally follow the steps provided by UG-1295 : " if the frequency step change is less than 100 MHz, and if the frequency step does not cross the VCO frequency break points ". the initial frequency 1 is 1.44GHz, the target frequency is 2GHz. below is my operations :
step 1 : TALISE_radioOff
step 2: TALISE_setRfPllFrequency and TALISE_getPllsLockStatus
step 3: TALISE_resetExtTxLolChannel
step 4: TALISE_radioOn
So we can get the total RF PLL lock time by ( step1 + step 2 + step 3 + step 4). in order to get the exact value, i also change the marco variables like "xxxSTATUS_INTERVAL_US" to 50 (50us) , so the time of each step is (50 * numEventChecks).
the question is : the step 1 and step 2 and step 3 cost little time like about 100us to 200us each .but the step 4 takes very long and the value is not stable, range from about 3msec to 20msec. I have no idea about why the time of step 4 is highly variable.
And i also did a test with only step 1 and step 4. At this time , the cost of step 4 is stable and only about 100us.
what is the reason of this result or how can i get the stable RF PLL lock time ?