ADRV9026 EVAL - Receive JESD profile

Hi,

For 4TX, I have chosen LMFS - 4841, which has 4 Serdes lanes, with 245.76MSPS rate and should address 4 DAC's.

Similarly for Receive I intend to have a profile with 4R with 4 lanes(no link sharing) and max sample rate 184.32MSPS. 

So, in ADRVTRX GUI only few profiles have been listed, which I chose 13_NLS profile.

Later, Since I need to have 4 lanes, I modified framer 0 to have 4 lanes and other fields automatically updated from GUI. So, this makes up LMFS - 4841

Then I took this init.c script from GUI and trying to bringup link between fpga and ADRV.

TX link is up and I could see waveforms on TXA and TXB, not sure TX3 and TX4 I am not seeing any waveforms, it has just junk coming on both ports. 

On ADC side, Sync is toggling, CGS->ILAS phase is in repeat mode, not sure why!

Is everything okay with above described profile and configs?

  • 0
    •  Analog Employees 
    on Dec 4, 2020 9:47 AM 2 months ago

    Are you able to program with the TES GUI after doing the changes?

    Have you changed the configuration on your FPGA side accordingly? Check the mismatch using the API: GetDfrmIlasMismatch()

  • Hi @srimoyi, thanks for the reply. We don't have host board to have GUI working. I just downloaded ADRV9026 TRX TRANSCEIVER S/W from website to have an overview and it has basic access and 3 Jesd profiles showing in demo mode. I am taking init.c file from the GUI after I set params in GUI. 

    Yes, for receive profile, I have set Jesd LMFS as per framer screenshot attached (4841)  above and lane rate is 4.9 Gbps. I am using common devclk and sysref for both Tx and Rx. Jesd Tx/Rx core clock is lanerate/40.

    Regarding Api will sure comeback with that. I am just starting to know about checking Jesd link errors through these Api's. Could you pls elaborate on how and where can I find about this?

    Also, with LMFS 4841 for TX, I could see waveforms on Tx1 and Tx2 ports but not on other two ports. Here  M=8 implies 4 DAC's right? But I could only see waveforms on Tx1 and Tx2 ports, not on other two ports. Can you pls suggest anything on this? 

    Thanks in advance.

  • 0
    •  Analog Employees 
    on Dec 8, 2020 11:59 AM 2 months ago in reply to rakshi

    From GUI, go to the help and then you can see list of all the API's in DLL help file. Under the ADRV9010DataInterface section, you can find all the JESD related API's.

    Check the status of the SYNC signal to check in which state the JESD is failing. Also check if all the TX are enabled by reading back using the API: RxTxEnableGet().

  • Hi , Thanks for the response. I have done tone tests on all DAC paths before even starting Jesd link tests and are fine. Able to see tones on all 4 paths.

    Regarding the API, RxTxEnableGet() is returning all 1's.

    So, again I am stuck. Can you pls tell what could be the problem? Some crossbar/lane problems or FPGA JESD TX core datapath issue? 

    I have even tried these observations with changing IQ data samples at TX JESD in fpga.

    My assumption is to send IQ of 32 bit to each antenna making it 128 bit input for 4 lanes.

    128 bit = {Tx4IQ,Tx3IQ,TX2IQ,TX1IQ}  Transmit JESD input.

    Cases tried :

    {Tx4IQ,Tx3IQ,TX2IQ,TX1IQ} - first two paths fine, TX3 and Tx4 just signal level raise.

    {Tx4IQ,Tx3IQ,TX2IQ,32'd0}  - No waveform seen on Tx1, TX2 fine, TX3 and Tx4 just signal level raise.

    {32'd0,Tx3IQ,TX2IQ,Tx1IQ}  -  Tx1 and TX2 fine, TX3 and Tx4 same signal level raise is observed. (strange)

  • 0
    •  Analog Employees 
    on Dec 8, 2020 4:36 PM 2 months ago in reply to rakshi

    One Question. 

    Since you are using 4 lanes, Each Tx will be on each lane from FPGA .

    Looks like you have mapped to 2 lanes from FPGA. Try sending Tx3 and Tx4 data and check Tx1 and Tx2 outputs.