ZCU102 with two ADRV9009 issues

Dear Team,

               we are using two ADRV9009 with ZCU102 . Two ADRV9009 are passing the basic initialization .But we are facing the below problems .

    1) In some power on's we are observing that link status is in CGS only( this was observed for 2 CH build ).

    2)For DAC I have done two test cases

         i) DAC data for each chip is generated with their respective clocks then transmitter outputs are as expected 

        ii) DAC data is generated using ADRV9009-1 and this data is also routed to ADRV9009-2 using asynchronous fifo .In this scenario transmitter output is deviated from the expected output .

            Screen shots are attached .What could be the reason for this 

/cfs-file/__key/communityserver-discussions-components-files/703/TWO_5F00_ADRV9009_5F00_TX_5F00_testing.docx

   Thanks in Advance  

  • 0
    •  Analog Employees 
    on Oct 23, 2020 9:43 AM 1 month ago
        1) In some power on's we are observing that link status is in CGS only( this was observed for 2 CH build ).

    Can you please share the framer and deframer status ? Please refer to the user guide UG-1295 for reading the framer and deframer status.

      2)For DAC I have done two test cases

    Attachment is missing. Can you please check? 

  • Thanks for the immediate response 

    Please find the attachment 

  • 0
    •  Analog Employees 
    on Oct 23, 2020 3:58 PM 1 month ago in reply to mourya_uts

    How are the device clock and sysref connected to the three devices. ?  Make sure Sysref reaches all 3 devices from same clock chip and same time.

    What is the SYNC status when the issue happens. 

    Please share TALISE_readFramerStatus () and TALISE_readDeframerStatus()

  • fail_prints.txt
    IIC PHY reset on ZCU102 successful 
    Hello
    rx_clkgen: MMCM-PLL locked (245760000 Hz)
    tx_clkgen: MMCM-PLL locked (245760000 Hz)
    rx_clkgen_0: MMCM-PLL locked (245760000 Hz)
    tx_clkgen_0: MMCM-PLL locked (245760000 Hz)
    rx_adxcvr: OK (9830400 kHz)
    tx_adxcvr: OK (9830400 kHz)
    rx_os_adxcvr: OK (9830400 kHz)
    rx_adxcvr_0: OK (9830400 kHz)
    tx_adxcvr_0: OK (9830400 kHz)
    rx_os_adxcvr_0: OK (9830400 kHz)
    warning: TALISE_enableMultichipSync() failed
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
    RF PLL frequency is 1000000000 talise: Calibrations completed successfully
    warning: TAL_DEFRAMER_A status 0x19
    warning: TAL_FRAMER_A status 0x20
    warning: TAL_FRAMER_B status 0x28
    warning: TALISE_enableMultichipSync() failed
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
    RF PLL frequency is 1000000000 talise: Calibrations completed successfully
    warning: TAL_DEFRAMER_A status 0x18
    warning: TAL_FRAMER_A status 0x20
    warning: TAL_FRAMER_B status 0x28
    rx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.790 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	LMFC rate: 7.680 MHz
    	Link status: DATA
    	SYSREF captured: No
    	SYSREF alignment error: No
    tx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.790 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	LMFC rate: 15.360 MHz
    	SYNC~: asserted
    	Link status: CGS
    	SYSREF captured: No
    	SYSREF alignment error: No
    rx_os_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.790 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	LMFC rate: 15.360 MHz
    	Link status: DATA
    	SYSREF captured: No
    	SYSREF alignment error: No
    rx_jesd_0 status:
    	Link is enabled
    	Measured Link Clock: 245.795 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	LMFC rate: 7.680 MHz
    	Link status: DATA
    	SYSREF captured: No
    	SYSREF alignment error: No
    tx_jesd_0 status:
    	Link is enabled
    	Measured Link Clock: 245.796 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	LMFC rate: 15.360 MHz
    	SYNC~: asserted
    	Link status: CGS
    	SYSREF captured: No
    	SYSREF alignment error: No
    rx_os_jesd_0 status:
    	Link is enabled
    	Measured Link Clock: 245.795 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	LMFC rate: 15.360 MHz
    	Link status: DATA
    	SYSREF captured: No
    	SYSREF alignment error: No
    
    tx_dac: Successfully initialized (491580200 Hz)
    tx_dac_0: Successfully initialized (491589355 Hz)
    
    rx_adc: Successfully initialized (245790100 Hz)
    rx_adc_0: Successfully initialized (245794677 Hz)