ADRV9009 Multiple sync ONLY with two situations

I try to synchronize 2 ADRV9009 IC(4 TX and 4 RX) named as ADRV9009_1 and ADRV9009_2 on single board.

I use ZYNQ7100 FPGA and clock IC to generate the two device_clk and two sysref signal to double ADRV9009, using the same clock IC to generate the ref_clk and sysref signal to FPGA.

The device_clk and sysref signal and ref_clk have the same phase.

The 12 steps to multiple_sync ADRV9009 has been running successfully with the right return value in the SDK with no-os project.

The device_clk of ADRV9009 is 122.88MHz and the sysref signal is 1.92MHz(122.88/64),according to the reference of AD9528, I used the pulse mode of sysref signal.

In the fpga project, NO mmcm is used for the core clk of jesd204b core IP and jesd204b PHY IP, BUT the difference with the ADI reference project is that I am using the Xilinx jesd 204b core and xilinx jesd204b PHY ip.

After the initialization of double adrv9009 and FPAG, I got two situations of the phase difference, one is phase sync correction and the other is that ADRV9009_1 has one sample point difference with ADRV9009_2.

I have set the value of F(the frame of jesd204b) as 4 and the value of K(multiple frame)as 32, after adjustment of lmfcOffset in the file of talise_config.c, I have got the safe LMFC boundary of jesd204b avoiding one LMFC difference of synchronization. 

I'm confused about the difference of one sample point with double ADRV9009! What setting would cause this error?


  • 0
    •  Analog Employees 
    on Oct 20, 2020 11:23 AM 1 month ago

    The FIFO depth readback should be at the medium of the depth else the latency between the systems will differ by one LMFC period. From UG:

    When establishing a JESD204B link, it is desirable that the data arriving to the deframer does not arrive very close to an LMFC boundary. If this does happen, the deterministic latency can vary from system to system if the data on one system arrives just before an LMFC event, and arrives on another system just after an LMFC event. If this happens, there is an LMFC period difference in the latency between the systems. Furthermore, the architecture in the device does not support a very small delay through the FIFO, and data corruption occurs if the delay is too small. Therefore, it is important that the FIFO depth be checked after the link is established, and the link is adjusted to achieve a FIFO depth that is close to the medium depth. The FIFO depth can be checked in Register 0x15CE for Deframer 0 and in Register 0x161E for Deframer 1. Write to the appropriate register with a value of 0x80 to latch the current FIFO depth, and then read back. The readback value is reported as a signed, twos complement number located in Bits[D5:D0] of the register with valid values from +K2 to −(K/2 − 1). The value reported is the difference of the number of frames between the read and write pointers. If the value is found to be close to 0, for example, −2, −1, 0, +1, or +2, adjust the depth by varying the LMFC offset parameter on either end of the JESD204B link. Note that across multiple system starts, the depth in the FIFO can vary by one or two frames. This variation is expected because sampling phase uncertainties are absorbed by the FIFO to give deterministic latency. Consider this fact when optimizing the JESD204B link and performing multiple system starts to find the worst case depth values for a given LMFC offset.

  • Thanks for your replay. I have read back the FIFO depth, the value jump between 64 and 60, both are at the medium of the depth of FIFO. Also if there is one LMFC period difference between double setup of my system, the phase difference would not be a sample point, but a multiple frame. Is that right?

  • 0
    •  Analog Employees 
    on Oct 21, 2020 9:09 AM 1 month ago in reply to Hans-li

    How are you measuring the phase sync between two boards? Please share details about your setup and the process of measurement.

    Are you seeing the phase shift between both the boards within a single boot(in run time)? with every boot are you seeing a constant phase difference?

    After the initialization of double adrv9009 and FPAG, I got two situations of the phase difference, one is phase sync correction

    Can you explain about the phase sync correction error that you are seeing?

  • I used 4RX channels of two ADRV9009 to simultaneously capture TWO different frequency tones(continuous), then using the raw data to compute the different phase of each channel, according to the two known frequency tones, I can compute how many samples each channel differ in the incomplete period.

    For example, if the first tone is 8 samples in one period, and the second tone is 256 samples in one period, then the phase difference of one samples of two tones is  2*pi/8 - 2*pi/256, so the distinction of samples would be computed using this formula.

    About your query, there is no phase shift between a single boot, the phase error is between -0.1~+0.1 radian.

  • 0
    •  Analog Employees 
    on Oct 28, 2020 8:25 AM 1 month ago in reply to Hans-li

    Can you check if the FIFO depth variation by 4 corresponds to the phase shift of +/-0.1rad variation? Are you seeing the phase difference when the FIFO depth doesnot change?