When designing with Ad9361, we can tune the oscillator using the dcxo_tune_coarse and dcxo_tune_fine attributes. As sampling clocks and LO frequency is synthesized from VCXO, we actually tune both LO and sampling clock.
Similarly while designing with ADRV9009 evaluation board, what should we do to tune LO and sampling clocks? Can we do it by tuning the 30.72MHz signal given to the Ref_clk_in sma of the evaluation board? Or should we tune onboard VCXO? If we need to tune VCXO, how can we do it?
You shall tune either the Ref clk or VCXO according to the offset frequency of each other.
What is the VCXO you are using? For tuning VCXO we recommend checking with the VCXO vendor.