We are going to use the ADRV9008-1 Receiver and AD9528 PLL chip in our design. We need some clarification regarding the sampling clock freq selection?. In ADRV9008-1 reference schematic(ADRV9008-1WPCBZ_Schematic_RevA), sampling clock is used as 122.88MHz and also the performance data is available with 61.44MHz sampling rate in the Datasheet. As per datasheet, the sampling clock range is 10 to 1000MHz.
1. Whether the sampling frequency selection should be in the order of 30.72, 61.44, 122.88MHz or integer value like 100, 200MHz.?
2. If i used the sampling frequency as 100MHz, any parameter will affect the receiver performance?
3. If sampling frequency selection should be in the order of 30.72, 61.44, 122.88MHz, pls suggest the PLL for 122.88MHz clk generation from 10/100MHz input freq.