I am new with JESD204B interface. I have a question about it.
Is length matching between JESD204B lanes required or not? As I read in some documents It's not required but I have doubts.
The length match between trace length is not a strict requirement in JESD204B, Subclass 1. The skew between the lanes are compensated using RX delay buffers,
Please refer to below link,
However, to maintain the deterministic latency across multiple devices it is recommended to have trace length matching for the syref, device clock, and sync signals.