One of four rx channels of two adrv9009s on one ZCU102 works badly, How?

Hi,

I am debuging two adrv9009s on one ZCU102. According some threads on this community, I have soved the clock distribution problem.

(https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/105981/two-adrv9009-eval-boards-on-zcu102)

After two adrv9009 were setuped, I found one channel can't work normally. The initialed log and the ila result were shown below. The I0 of the second adrv9009 (the slave one with sysref bypass) can't woks well. No matter what signal gived from signal generator, it stays the same.

But in another test, the log information and ila result were show below. The I0 and Q0 of the second adrv9009(namely RX1 Channel) (the slave one with sysref bypass) both works badly.

Could you tell me How shoud I to check the problem?

  • 0
    •  Analog Employees 
    on Apr 26, 2020 6:17 PM 7 months ago

    Could you explain your system a bit more.

    You have two ZCU102 FPGA boards and both have one ADRV9009 connected. 

    You are giving Sysref and devclock from master (say A) ADRv9009 to slave (say B) ADRV9009.

    Master (A) ADRV9009 works fine but slave ADRV9009 is not working. Is my understanding correct ?

    But in another test, the log information and ila result were show below. The I0 and Q0 of the second adrv9009(namely RX1 Channel) (the slave one with sysref bypass) both works badly.

    What do you mean by another test ?  Same setup if you run again , it is working fine ? 

    Are you using continuous sysref  ?

    When you are programming the two boards are you programming the two boards together (same time) ?

    Framer status is 07, SYSREF phase error, a new SYSREF had different timing than the first that set the LMFC timing.

    Check sysref signal reaching salve (B) ADRV9009 and make sure that It aligns with master ADRV9009 Sysref. 

  • Hi Vinod,

    sorry for reply later.Great thanks.

    I will descripe my system again. My hardware are as below, using one ZCU102 holding two adrv9009s.

    and the mater board(namely the Board 1 in the below fig) use OUT5/OUT7/OUT8 to create FPGA_REFCLK/SYSREF/ADRV_REFCLK for the slave one(namely the Board 2 in the below fig).

    The sysref of adrv9009 on Board 2 is from the master one with the 9528 bypass like the fig above.

    The sysref are all 0.12MHz.

    I am using continuous sysref. And the ad9528_sysref_req control signals from FPGA are both collected to the ad9528 of the master one. 

    when the ad9528_sysref_req is High, like the function below,

    I can probe continues waves with frequency of 0.12MHz with oscilloscope on each port of sysref.

    ---------------------------------------------------------------------------------------------------------------------------------------------

    Question 1:

    Answer 1 :I said another test, means power down and power up again. Just same setup, and  run again but with different results.

    Question 2:

    Answer 2: Yes, I am using continuous sysref.

    Question 3:

    Answer 3: I am using one zcu102 + two adrv9009s, and Initialed master adrv9009 first and then the second one.

    you said I need to "Check sysref signal reaching salve (B) ADRV9009 and make sure that It aligns with master ADRV9009 Sysref. " 

    How to check? With Oscilloscope to probe the two signal at same time? and the rising-edges of both sysrefs  should aligned,is it right?

    One more question, how to deal with the ad9528_sysref_req signals? I connected both ad9528_sysref_req signals to the ad9528 on the mater board, is it right?

  • 0
    •  Analog Employees 
    on Apr 30, 2020 5:10 AM 7 months ago in reply to fengzutian
    How to check? With Oscilloscope to probe the two signal at same time? and the rising-edges of both sysrefs  should aligned,is it right?

    Yes correct

    One more question, how to deal with the ad9528_sysref_req signals? I connected both ad9528_sysref_req signals to the ad9528 on the mater board, is it right?

    Since you are bringing up one ADRv9009 at a time this is Ok.

    Answer 1 :I said another test, means power down and power up again. Just same setup, and  run again but with different results.

    This can be due to incorrect sysref. Check for JESD status. Also you can check FIFO depth on each boot and check if it is varying more than 1. 

    it is important that the FIFO depth be checked after the link is established, and the link is adjusted to achieve a FIFO depth that is close to the medium depth. The FIFO depth can be checked in Register 0x15CE for Deframer 0 and in Register 0x161E for Deframer 1. Write to the appropriate register with a value of 0x80 to latch the current FIFO depth, and then read back.

  • Thanks a lot.

    I will check the timing of the sysref of the Two adrv9009s, and then check the FIFO depth according your instructions. I will response to you later.

  • Hi Vinod, sorry for reply late.

    According your instructions, I check the timing of the sysref of the two adrv9009s and found something wrong.

    I probed the master adrv9009 first and found the sysrefs to fpga and to adrv9009 are synced and stable.

    Then I probed the slave one, and found the sysrefs to fpga and to adrv9009 were not stable, like the figure below, the square wave was not stable.

    Then I probed the sysref_in clock to ad9528 and its output sysref to adrv9009, I found the sysref_in clock to ad9528 was ok, and its output sysref clock to fpga and adrv9009 were wrong, like the figure below. The pink wave was the sysref_in clock to ad9528, and the green one was the clock to adrv9009 on the slave board.

     

    So I want to ask, how to set the ad9528 on the slave board to make the output sysref clokc ok?