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What reasons may cause the jesd204b rx_link status stop at CGS state?

Thanks in advance.

I am debuging two adrv9009_evals on single ZCU102, the debug information are as below.

there is a warning indicates that TAL_FRAMER_A status is 0x01, I checked the 1295pdf, and find 

but I don't know what does SYSREF phase error means.

the sysref clk of adrv9009 and FPGA are both 0.12MHz, how could this error happen?

  • Are you using continuous Sysref or single shot? Are you seeing this issue on both Transceivers.?

    I guess your setup is having 2 ADRV9009 boards and using Sysref from one board as reference. Is my understanding correct.

    Have you checked Sysref timing on  both devices ?

  • Great thanks for your reply.

    I am using continuous Sysref. The HDL project is based on the prototype_som branch of the github as below. 

    Yes, indeed. I am planing to use the Sysref from the talise on HPC0 as reference shown below.

    And the first step, based on the hdl project, I just initialed the talise device on HPC0, as below.

    However the project failed with the errors staying in CGS state.

    I checked the sysref_req signal, and when it is logic High, the sysref comes up with frequency of 120kHz, and when it is logic Low, there's no sysref clk. So the sysref is working well. 

    So where is the problem?

    Thanks again. 

  • Hope ypu are using one AD9528 as clock source for both evaluation boards as explained in the later part of below post. (just to confirm)

    https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/105981/two-adrv9009-eval-boards-on-zcu102 

    Have you checked dev clock and Sysref timing with oscilloscope on both the second board w.r.t first. You may need to adjust the delay to match timing.

    What is the JESD frame/deframer  status showing for both device. The first device where the AD9528 is used , is that working fine.?

  • I need explain more clearly.

    yes, I was planing to use one AD9528 as clock source for both evaluation boards as below scheme in your given post.

    but now, the first step, I am just debuging the first device where the ad9528 is used, and I havn't given sysref and device clk to adrv9009 on the second board and also I didn't initial the second device through spi. So there's no JESD frame/deframer  status about the second device.

    And the state information of first device is below, the rx link can't be set up.

     I checked Sysref of the first device with oscilloscope, and found it was indeed 0.12Mhz. but there's the CGS state error.

    Can you give some advice what should I do next?

  • With the GUI software , Is the board working as expected. ?

    What is the status of SYNC signal , is it asserted or toggling ?

    JESD can be struck in CGS phase due to below reasons.

    1. Signal integrity issues. I guess this can be ruled out as its direct eval board connected to FPGA. Known working hardware.

    2. The parameters configured on both sides of FPGA link are different. You can check if all the paramerts configured are same on both sides,

    3. Lane rates and number of lanes are different or two different clocks are used on FPGA and Transceiver side.

  • Hi, Vinod, with your instruction, I have run all the necessary clokcs well. I probed the sysref of the first adrv and the second adrv with the oscilloscope and find that its frequency is indeed 0.12MHz continues wave when sysref_req was '1'.
    Under this clock distrubution, I tried  to initial the two  adrv9009s, the initialed log is shown as below.
    //------------------------------------------------------------------------//
    Hello
    rx_clkgen: MMCM-PLL locked (245760000 Hz)
    tx_clkgen: MMCM-PLL locked (122880000 Hz)
    rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
    rx_adxcvr: OK (9830400 kHz)
    tx_adxcvr: OK (4915200 kHz)
    rx_os_adxcvr: OK (4915200 kHz)
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.527765581332480005
    talise: Calibrations completed successfully
    warning: TAL_FRAMER_A status 0x1
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.527765581332480005
    talise: Calibrations completed successfully
    warning: TAL_FRAMER_A status 0x7
    rx_jesd: Lane 2 desynced (26 errors), restarting link
    rx_jesd: Lane 3 desynced (9 errors), restarting link
    rx_os_jesd: Lane 2 desynced (6 errors), restarting link
    rx_os_jesd: Lane 3 desynced (1663 errors), restarting link
    rx_jesd status:
    Link is enabled
    Measured Link Clock: 245.775 MHz
    Reported Link Clock: 245.760 MHz
    Lane rate: 9830.400 MHz
    Lane rate / 40: 245.760 MHz
    LMFC rate: 7.680 MHz
    Link status: DATA
    SYSREF captured: Yes
    SYSREF alignment error: No
    tx_jesd status:
    Link is enabled
    Measured Link Clock: 122.888 MHz
    Reported Link Clock: 122.880 MHz
    Lane rate: 4915.200 MHz
    Lane rate / 40: 122.880 MHz
    LMFC rate: 7.680 MHz
    SYNC~: deasserted
    Link status: DATA
    SYSREF captured: Yes
    SYSREF alignment error: No
    rx_os_jesd status:
    Link is enabled
    Measured Link Clock: 122.888 MHz
    Reported Link Clock: 122.880 MHz
    Lane rate: 4915.200 MHz
    Lane rate / 40: 122.880 MHz
    LMFC rate: 7.680 MHz
    Link status: DATA
    SYSREF captured: Yes
    SYSREF alignment error: No
    tx_dac: Successfully initialized (245773315 Hz)
    rx_adc: Successfully initialized (245774841 Hz)
    //------------------------------------------------------------------------//
    Two questions I want to ask:
    1: from the jesd status, the link statuses of rx_jesd, tx_jesd and orx_jesd are all DATA state, does it link setup ok? If so, Do I need to try to solve the following errors:

    If you think the initialed progress is failed, how should I do next?

    2:  After above initialed process, I probe the tx rx and orx sync signals, and find they are all HIGH, shown as below.

    Is it right?

  • Farmer status is 07 : SYSREF phase error, a new SYSREF had different timing than the first that set the LMFC timing.

    Can you try single shot sysref?

    IS this custom board ? If custom you may need to check for Signal integrity of link as well.

    You can use PRBS generator and checker to test the interface. User guide has more details,

  • Thanks, I will try single shot sysref later.

    Just set the master 9258 output single shot sysref, is it right?

    I am using ZCU102 + adrv9009.

  • Just set the master 9258 output single shot sysref, is it right?

    Yes.