ADRV9009 decoupling capacitors

Hello,
I am wondering if there is a table of recommended values or minimums for decoupling caps for the ADRV9009 transceiver. In particular I am wondering about the 1.3V analog power rails. 

VDDA1P3_RF_LO, VDDA1P3_RF_SYNTH,VDDA1P3_AUX_SYNTH etc. Looking at the ADRV9009 eval card most of these power inputs have significant decoupling caps, VDDA1P3_RF_SYNTH has 2X 220uf for example which is quite a bit. Can anyone point me to a table of recommended values for all of the ADRV9009 transceiver power inputs. Thank for any help provided. 

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  • 0
    •  Analog Employees 
    on Apr 16, 2019 9:25 AM

    Recommendation is to follow the reference schematics. If you are using in TDD mode , the higher value capacitors help to provide peak currents and reduce switching transience.

    May be you can provide all capacitors in initial design and later remove them and study impact. If in your system there is no impact you car make them DNI.

  • What is the average and peak current for each of these rails (VDDA1P3_RF_LO, VDDA1P3_RF_SYNTH and VDDA1P3_AUX_SYNTH)?

    The VDDA1P3_RF_SYNTH rail has ferrite beads E602 and E613 in series which have very high DC resistance. These are followed by the 2x220uF, 1x1uF and 1x0.1uF caps. The large caps reduce the effect of ESR of the FBs at low frequency. 

    I am assuming filtering is to improve PSRR (source is DC-DC converter) and isolation from other VDDA1P3 rails which are using common VDDA1P3_ANLG rail.

    The VDDA1P3_RF_LO has 0.1ohm resistor in series with the 3x220uF and 1x1uF caps. It seems odd that there are no high frequency bypass caps on this pin. I though there would be noise at the 1xLO and/or 2xLO frequency on this pin. 

    Do these rails have internal linear regulators? If not I think a better solution for low noise would be to use RF linear regulator with post filtering for these rails. This would improve low frequency PSRR and potentially allow use of single FB and smaller caps.

    What is the peak current for the VDDA1P3_SER rail?

  • 0
    •  Analog Employees 
    on Oct 4, 2019 5:45 AM in reply to gavolbs

    Typical peak currents are as below.

    Current (A) PIN (V) Typ Peak current(A)
    VDDA_1P3_BB E5 1.3 0.635
    VDDA_1P3_CLK_LDO N1 1.3 0.172
    VDDA_1P3_RX_RF B1 1.3 0.058
    VDDA_1P3_AUX_VCO_LDO C10 1.3 0.154
    VDDA_1P3_CLK_SYNTH G5 1.3 0.003
    VDDA_1P3_RX_TX C3 1.3 0.268
    VDD_1P3_DIG L8,L9 1.3 1.588
    VDDA_1P3_RF_VCO_LDO C5,C6 1.3 0.255
    VDDA_1P3_DES N9,P9 1.3 0.242
    VDDA_1P3_SER N8,P8 1.3 0.119
    VDDA_1P3_RFLO C8 1.3 0.055
    VDDA_1P3_AUX_SYNTH G8 1.3 0.008
    VDDA_1P3_RF_SYNTH G7 1.3 0.009

    You can add linear regulators as required , I guess we have used ADP1763 in our initial designs and in evaluation board to reduce BOM cost we removed them. It will be good to have them as you suggested.

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  • 0
    •  Analog Employees 
    on Oct 4, 2019 5:45 AM in reply to gavolbs

    Typical peak currents are as below.

    Current (A) PIN (V) Typ Peak current(A)
    VDDA_1P3_BB E5 1.3 0.635
    VDDA_1P3_CLK_LDO N1 1.3 0.172
    VDDA_1P3_RX_RF B1 1.3 0.058
    VDDA_1P3_AUX_VCO_LDO C10 1.3 0.154
    VDDA_1P3_CLK_SYNTH G5 1.3 0.003
    VDDA_1P3_RX_TX C3 1.3 0.268
    VDD_1P3_DIG L8,L9 1.3 1.588
    VDDA_1P3_RF_VCO_LDO C5,C6 1.3 0.255
    VDDA_1P3_DES N9,P9 1.3 0.242
    VDDA_1P3_SER N8,P8 1.3 0.119
    VDDA_1P3_RFLO C8 1.3 0.055
    VDDA_1P3_AUX_SYNTH G8 1.3 0.008
    VDDA_1P3_RF_SYNTH G7 1.3 0.009

    You can add linear regulators as required , I guess we have used ADP1763 in our initial designs and in evaluation board to reduce BOM cost we removed them. It will be good to have them as you suggested.

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