Two ADRV9009 and two ZCU102

I read following post:

But when I am targeting two completely independent boards (or more), the boards will have it's own FPGA (multiple ZCU102 boards). How can I manage that the platforms are time and phase coherent?

Beside the suggestion from previous post ( "skip the second AD9528 and take out sysref and devclk"), what else should I do? Make an extra connection to the other FPGA boards driving the FPGA_REF_CLK and FPGA_SYSREF? But how can I solve the signals towards the AD9528? CLK_SYSREF_REQUEST and the SYSREF_CLK_IN?

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  • Filter wizard, new API, and user guide

    Nice tool!

    I noticed in the release notes:

    • New APIs:
      • New API to support RF LO Sync (TALISE_enableMultichipRfLOPhaseSync) to be used in initsequeneceinstead of previous MCS function.Slightly different device initsequence. The previous MCS function is still valid if RF LO Sync is not required.
      • Added TALISE_serializerReset().It should be called after MCS to reset clock dividers at serializer.This is called automatically in backward support initcases (called in TALISE_enableMultichipSyncwhen enableMcsparameter = 0) , but exposed incase needed for a custom initsequence or using TALISE_enableMultichipRfLOPhaseSync.
      • Added API to enable/disable Digital DC offset

    Is it already available in IIO-oscilloscope API? I didn't see any updates there? Which API do you mean?

    Or is it only accessible trough the linux virtual file IO? In that case I probably need to update my linux kernel drivers?

    So, how can I test those new features? I have a ZCU102 board and the ADRV9009-W/PCBZ