I read following post: https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/105981/two-adrv9009-eval-boards-on-zcu102
But when I am targeting two completely independent boards (or more), the boards will have it's own FPGA (multiple ZCU102 boards). How can I manage that the platforms are time and phase coherent?
Beside the suggestion from previous post ( "skip the second AD9528 and take out sysref and devclk"), what else should I do? Make an extra connection to the other FPGA boards driving the FPGA_REF_CLK and FPGA_SYSREF? But how can I solve the signals towards the AD9528? CLK_SYSREF_REQUEST and the SYSREF_CLK_IN?
From UG-1295,
I still have a few questions:
Refer https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/105981/two-adrv9009-eval-boards-on-zcu102/314375#314375
1. Hope above answers.
2. JESD in ACU102 as well needs to be configured for the link to be successful.
3. The MCS function needs to be called for multichip synchronization. There is a new SW release coming positively by 6th Feb, 2019 which has improved the MCS functionality. Please refer the corresponding section in user guide for details on functionality of MCS.
Vinod said:The MCS function needs to be called for multichip synchronization. There is a new SW release coming positively by 6th Feb, 2019 which has improved the MCS functionality. Please refer the corresponding section in user guide for details on functionality of MCS.
Any news?
Filter wizard, new API, and user guide have been handed over to the web team. Should be released by next week.
Please download the filter wizard tool from below link.
https://www.analog.com/en/design-center/landing-pages/001/transceiver-evaluation-software.html