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Two ADRV9009 and two ZCU102

I read following post:

But when I am targeting two completely independent boards (or more), the boards will have it's own FPGA (multiple ZCU102 boards). How can I manage that the platforms are time and phase coherent?

Beside the suggestion from previous post ( "skip the second AD9528 and take out sysref and devclk"), what else should I do? Make an extra connection to the other FPGA boards driving the FPGA_REF_CLK and FPGA_SYSREF? But how can I solve the signals towards the AD9528? CLK_SYSREF_REQUEST and the SYSREF_CLK_IN?

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