I read following post: https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/105981/two-adrv9009-eval-boards-on-zcu102
But when I am targeting two completely independent boards (or more), the boards will have it's own FPGA (multiple ZCU102 boards). How can I manage that the platforms are time and phase coherent?
Beside the suggestion from previous post ( "skip the second AD9528 and take out sysref and devclk"), what else should I do? Make an extra connection to the other FPGA boards driving the FPGA_REF_CLK and FPGA_SYSREF? But how can I solve the signals towards the AD9528? CLK_SYSREF_REQUEST and the SYSREF_CLK_IN?
I still have a few questions:
1. Hope above answers.
2. JESD in ACU102 as well needs to be configured for the link to be successful.
3. The MCS function needs to be called for multichip synchronization. There is a new SW release coming positively by 6th Feb, 2019 which has improved the MCS functionality. Please refer the corresponding section in user guide for details on functionality of MCS.
Thanks that sounds great!
Two more questions:
1. Meanwhile we or working on a board design. Can you advise if following configuration is possible?
2. From the user guide I get this:
Once this mode is enabled on both ZCU102 platforms. Is it enough to run the four SYSREF pulses from the external AD9528 EVM board? And check mcsStatus to check if synchronization has completed?
1. It will be better if you can supply clocks for all devices directly from AD9528 Eval and by passing AD9528 in ADRV9009 board.
2. Yes 4 sysref to each device should be sufficient.
1. In our product configuration, we are targeting on 3 separated 19" units (one clock distribution unit, and multiple ADRV9009 based units). If we bypass the extra AD9528's, we will loos the clock clean up feature. So if it is possible then we prefer to keep the extra AD9528 and use it as buffer.
2. Do I need to enable the "enableMCS" first prior to send the 4 consecutive pulses?
1. If you are designing your system , you can connect multiple devices from single AD9528. It has 14 clk outs and max 7 devices can be connected.
2. 3 sysref needs to be send after calling TALISE_enableMultichipSync with enabe 1. 1 sysref is supplied during JESD
1. What can I do for clock clean up? The REF_CLK_IN is also the reference for the Rf synthesizer. So, if noise or other spurs are picked up (because devices needs to be synced in different 19" units) it should be cleaned close to the ADRV9009. Phase noise is very important in my application.
if you see issues at system level then you may need to address them accordingly. you may need to conider performance vs cost as well.
To clean up clock you may have to go with additional jitter cleaner with delay adjustment option like AD9528.