I read following post: https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/105981/two-adrv9009-eval-boards-on-zcu102
But when I am targeting two completely independent boards (or more), the boards will have it's own FPGA (multiple ZCU102 boards). How can I manage that the platforms are time and phase coherent?
Beside the suggestion from previous post ( "skip the second AD9528 and take out sysref and devclk"), what else should I do? Make an extra connection to the other FPGA boards driving the FPGA_REF_CLK and FPGA_SYSREF? But how can I solve the signals towards the AD9528? CLK_SYSREF_REQUEST and the SYSREF_CLK_IN?
I still have a few questions: