I want to use two ADRV9009 Eval Boards on ZCU102.
ZCU102 has two FMC(HPC) connectors.
Is it possible to run two ADRV9009 Eval Boards?
Synchronization of data between two ADRV9009 chips will be OK?
Please refer to the below post:
Refer to the RFPLL phase synchronization section in UG for more details on MCS.
Hi Srimoyi and Tobe,
The given URL just confirms that we can use 2 ADRV9009s on ZCU102, but does not mention about the data synchronization between 2 boards.
In my case, I have built two separated versions - one ADRV9009 on HPC1 , the other on HPC0. Both version works flawlessly. But when combing them to create a version for 2 ADRV9009, it does not work anymore. JESD204 link cannot establish. I am investigating issues may cause this problem.
For data synchronization between 2 boards, I think they should be sourced from a common clock source for device clock and SYSREF. Do you have any further constraint for 2-boards synchronization?
The following picture is our data link layer:
Datalink layer is enabled when receiving SYNC from ADRV9009 (in the picture, the signal is tx_sync).
For the HDL part of ADI framework,
From those points, I think it is possible to use only one DATALINK layer for both ICs (or I just need only one SYSREF for FPGA side).
Do you have any comment?
Thanks and Regards,
I am not an expert to comment here. So both the FPGA's are on single board and one is master and other is slave.
andrei_g Any comments.
Vinod yes, both FPGA are on single board
Hi,A single link layer should work.Your sync setup is good.Andrei
thanks for your confirmation