Two ADRV9009 EVAL Boards on ZCU102

Hi Support,

I want to use two ADRV9009 Eval Boards on ZCU102.

ZCU102 has two FMC(HPC) connectors.

Is it possible to run two ADRV9009 Eval Boards?

Synchronization of  data between two ADRV9009 chips will be OK?

Best Regards.

Tobe 

Parents Reply
  • Hello Vinod,

    The following picture is our data link layer:

    Datalink layer is enabled when receiving SYNC from ADRV9009 (in the picture, the signal is tx_sync).

    In fact,

    • tx_sync = tx_sync_adrv9009_board1 && tx_sync_adrv9009_board2
    • rx_sync and orx_sync are distributed to 2 boards through their FMC port.

    For the HDL part of ADI framework,

    • ADI JESD204 Receive / Transmitter supports up to 8 lanes, that means it is possible to use ONE

      IPCORE for 2 ADRV9009.
    • ADI JESD204 PHY (util_adxcvr) supports up to 16 lanes or up to 4 ADRV9009 IC.

    From those points, I think it is possible to use only one DATALINK layer for both ICs (or I just need only one SYSREF for FPGA side).

    Do you have any comment?

    Thanks and Regards,

    Trung Nguyen

Children
  • 0
    •  Analog Employees 
    on Feb 14, 2019 11:22 AM over 1 year ago in reply to trungnguyen

    I am not an expert to comment here. So both the FPGA's are on single board and one is master and other is slave. 

    Any comments. 

  • 0
    •  Analog Employees 
    on Feb 15, 2019 8:42 AM over 1 year ago in reply to trungnguyen

    Hi,

    A single link layer should work.
    Your sync setup is good.

    Andrei

  • Hi Andrei,

    thanks for your confirmation

    Trung Nguyen

  • I used 8 TX lanes for two adrv9009. First 4 TX lanes connected with HPC1. When I connect other 4 tx lanes with HPC0 the I find GTH Transceiver Error "



    [Place 30-739] Sub-optimal placement for an IBUFDS_GT / GT component pair.Processing will continue as all instances of this rule have been LOCed.

        i_ibufds_ref_clk1 (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X0Y3
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_1/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y12
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_5/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y10
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_4/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y9
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_3/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y15
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y14
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y13
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_7/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y8
         and i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_6/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y11
    [Place 30-739] Sub-optimal placement for an IBUFDS_GT / GT component pair.Processing will continue as all instances of this rule have been LOCed.

        i_ibufds_ref_clk1 (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X0Y3
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_1/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y12
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_5/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y10
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_4/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y9
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_3/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y15
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y14
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y13
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_7/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y8
         and i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_6/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y11
    [Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
        < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xcm_4/qpll2ch_clk] >

        i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xcm_4/i_gthe4_common (GTHE4_COMMON.QPLL0OUTCLK) is provisionally placed by clockplacer on GTHE4_COMMON_X0Y1
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_5/i_gthe4_channel (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X1Y10
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_4/i_gthe4_channel (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X1Y9
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_7/i_gthe4_channel (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X1Y8
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_6/i_gthe4_channel (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X1Y11

        The above error could possibly be related to other connected instances. Following is a list of
        all the related clock rules and their respective instances.

        Clock Rule: rule_bufds_gthchannel_intelligent_pin
        Status: FAIL
        Rule Description: A BUFDS driving a GTHChannel must both be placed in the same or adjacent two clock
        regions (top/bottom)
         i_ibufds_ref_clk1 (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X0Y3
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_1/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y12
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_5/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y10
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_4/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y9
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_3/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y15
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y14
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y13
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_7/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y8
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_6/i_gthe4_channel (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y11
        ERROR: The above is also an illegal clock rule
        Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ref_clk1] >

        Clock Rule: rule_bufds_gthcommon_intelligent_pin
        Status: PASS
        Rule Description: A BUFDS driving a GTHCommon must both be placed in the same or adjacent two clock
        regions (top/bottom)
         i_ibufds_ref_clk1 (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X0Y3
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xcm_0/i_gthe4_common (GTHE4_COMMON.GTREFCLK00) is provisionally placed by clockplacer on GTHE4_COMMON_X0Y3
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xcm_4/i_gthe4_common (GTHE4_COMMON.GTREFCLK00) is provisionally placed by clockplacer on GTHE4_COMMON_X0Y1

        Clock Rule: rule_gthcommon_gthchannel
        Status: PASS
        Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xcm_0/i_gthe4_common (GTHE4_COMMON.QPLL0OUTCLK) is provisionally placed by clockplacer on GTHE4_COMMON_X0Y3
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_1/i_gthe4_channel (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X0Y12
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_3/i_gthe4_channel (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X0Y15
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/i_gthe4_channel (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X0Y14
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_gthe4_channel (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X0Y13

        Clock Rule: rule_gt_bufggt
        Status: PASS
        Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
        BUFG
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_gthe4_channel (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y13
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_rx_bufg (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X0Y95

        Clock Rule: rule_gthchannel_bufgsync_rx
        Status: PASS
        Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
        both have to be in specific sites.
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_gthe4_channel (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y13
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/BUFG_GT_SYNC (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y49

        Clock Rule: rule_gthchannel_bufgsync_tx
        Status: PASS
        Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
        both have to be in specific sites.
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_gthe4_channel (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y13
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/BUFG_GT_SYNC_1 (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y47

        Clock Rule: rule_gt_bufggt
        Status: PASS
        Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
        BUFG
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/i_gthe4_channel (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y14
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/i_rx_bufg (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X0Y93

        Clock Rule: rule_gthchannel_bufgsync_rx
        Status: PASS
        Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
        both have to be in specific sites.
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/i_gthe4_channel (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y14
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/BUFG_GT_SYNC (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y55

        Clock Rule: rule_bufgsync_bufg_withGTDriver
        Status: PASS
        Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
        as the BUFG_GT
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/BUFG_GT_SYNC (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y49
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_rx_bufg (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y95

        Clock Rule: rule_bufgsync_bufg_withGTDriver
        Status: PASS
        Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
        as the BUFG_GT
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/BUFG_GT_SYNC_1 (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y47
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_0/i_tx_bufg (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y94

        Clock Rule: rule_bufgsync_bufg_withGTDriver
        Status: PASS
        Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
        as the BUFG_GT
         i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/BUFG_GT_SYNC (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y55
         and i_system_wrapper/system_i/util_adrv9009_p_som_xcvr/inst/i_xch_2/i_rx_bufg (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y93

    [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
    Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
    [Common 17-69] Command failed: Placer could not place all instances