I want to use two ADRV9009 Eval Boards on ZCU102.
ZCU102 has two FMC(HPC) connectors.
Is it possible to run two ADRV9009 Eval Boards?
Synchronization of data between two ADRV9009 chips will be OK?
Yes Correct. There will be some DNI which you need to populate and may be remove few components to disconnect existing clocks.
Please refer USer guide UG 1295 section on RF PLL Phase Synchronization Demo Setup with 2 Two Evaluation Platforms
In this case you can skip the second AD9528 and take out sysref and devclk from first AD9528 via the schematic snapshot you copied above and feed directly to next AD9371.
Any of the 14 outputs of AD9528…
Please refer to the below post:
Refer to the RFPLL phase synchronization section in UG for more details on MCS.
Hi Srimoyi and Tobe,
The given URL just confirms that we can use 2 ADRV9009s on ZCU102, but does not mention about the data synchronization between 2 boards.
In my case, I have built two separated versions - one ADRV9009 on HPC1 , the other on HPC0. Both version works flawlessly. But when combing them to create a version for 2 ADRV9009, it does not work anymore. JESD204 link cannot establish. I am investigating issues may cause this problem.
For data synchronization between 2 boards, I think they should be sourced from a common clock source for device clock and SYSREF. Do you have any further constraint for 2-boards synchronization?
Everything is clear. Thanks for supports.
is it really ok to skip the second AD9528? Would the second AD9528 still provide SYSREF/REFCLK to the FPGA side? In other words : can the SYSREF/REFCLK for the FPGA side come from 1 PLL, and the SYSREF/REFCLK for the ADRV9009 side come from 2 different PLLS? (which do have the same ref clock I guess, but still it looks a bit tricky?)
In my case, the followingis my setup (I am testing it)
- The second AD9528 doesn't provide REFCLK to FPGA. REFCLK is taken from the first AD9528. But it needs to route from the first board to the second board, then to FPGA through FMC port (to provide REF for GT Transceiver)
- SYSREF for AD9009 on the second board, on the other hand, is still provided by the second AD9528 (in bypass mode - source is from 1st AD9528), then I can adjust its delay.
- SYSREF for FPGA side just need to be taken from 1st AD9528.
P/S: I think you should start another thread, so we can discuss further and get more support from ADI.
may be you can go with below option
My setup is nearly the same with yours.
The only difference is " I have only one SYSREF for FPGA side which is taken from the 1st AD9528".
Do we really need the second FPGA SYSREF (from 2nd AD9528)?
As I understand, having 2 FPGA SYSREF forces us to separate DATA LINK LAYER of FPGA1 and FPGA2 where handling link alignment process. However, we, in fact, need the same link latency for both interfaces, so it just need only ONE data link layer for both. Is that right?
The following is my scheme:
How will you enable single datalink layer for both ?
The following picture is our data link layer:
Datalink layer is enabled when receiving SYNC from ADRV9009 (in the picture, the signal is tx_sync).
For the HDL part of ADI framework,
From those points, I think it is possible to use only one DATALINK layer for both ICs (or I just need only one SYSREF for FPGA side).
Do you have any comment?
Thanks and Regards,
I am not an expert to comment here. So both the FPGA's are on single board and one is master and other is slave.
andrei_g Any comments.
Vinod yes, both FPGA are on single board
Hi,A single link layer should work.Your sync setup is good.Andrei