Two ADRV9009 EVAL Boards on ZCU102

Hi Support,

I want to use two ADRV9009 Eval Boards on ZCU102.

ZCU102 has two FMC(HPC) connectors.

Is it possible to run two ADRV9009 Eval Boards?

Synchronization of  data between two ADRV9009 chips will be OK?

Best Regards.


Parents Reply
  • Hello Vinod,

    My setup is nearly the same with yours.

    The only difference is " I have only one SYSREF for FPGA side which is taken from the 1st AD9528".

    Do we really need the second FPGA SYSREF (from 2nd AD9528)?

    As I understand, having 2 FPGA SYSREF forces us to separate DATA LINK LAYER of FPGA1 and FPGA2 where handling link alignment process. However, we, in fact, need the same link latency for both interfaces, so it just need only ONE data link layer for both. Is that right? 

    The following is my scheme:

    Best Regards,

    Trung Nguyen