Two ADRV9009 EVAL Boards on ZCU102

Hi Support,

I want to use two ADRV9009 Eval Boards on ZCU102.

ZCU102 has two FMC(HPC) connectors.

Is it possible to run two ADRV9009 Eval Boards?

Synchronization of  data between two ADRV9009 chips will be OK?

Best Regards.


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  • Hello,

    In my case, the followingis my setup (I am testing it)

    - The second AD9528 doesn't provide REFCLK to FPGA. REFCLK is taken from the first AD9528. But it needs to route from the first board to the second board, then to FPGA through FMC port (to provide REF for GT Transceiver)

    - SYSREF for AD9009 on the second board, on the other hand, is still provided by the second AD9528 (in bypass mode - source is from 1st AD9528), then I can adjust its delay.

    - SYSREF for FPGA side just need to be taken from 1st AD9528.

    P/S: I think you should start another thread, so we can discuss further and get more support from ADI.


    Trung Nguyen

  • 0
    •  Analog Employees 
    on Feb 11, 2019 7:04 AM in reply to trungnguyen

    may be you can go with below option

  • Hello Vinod,

    My setup is nearly the same with yours.

    The only difference is " I have only one SYSREF for FPGA side which is taken from the 1st AD9528".

    Do we really need the second FPGA SYSREF (from 2nd AD9528)?

    As I understand, having 2 FPGA SYSREF forces us to separate DATA LINK LAYER of FPGA1 and FPGA2 where handling link alignment process. However, we, in fact, need the same link latency for both interfaces, so it just need only ONE data link layer for both. Is that right? 

    The following is my scheme:

    Best Regards,

    Trung Nguyen

  • 0
    •  Analog Employees 
    on Feb 13, 2019 2:22 PM in reply to trungnguyen

    How will you enable single datalink layer for both ?

  • Hello Vinod,

    The following picture is our data link layer:

    Datalink layer is enabled when receiving SYNC from ADRV9009 (in the picture, the signal is tx_sync).

    In fact,

    • tx_sync = tx_sync_adrv9009_board1 && tx_sync_adrv9009_board2
    • rx_sync and orx_sync are distributed to 2 boards through their FMC port.

    For the HDL part of ADI framework,

    • ADI JESD204 Receive / Transmitter supports up to 8 lanes, that means it is possible to use ONE

      IPCORE for 2 ADRV9009.
    • ADI JESD204 PHY (util_adxcvr) supports up to 16 lanes or up to 4 ADRV9009 IC.

    From those points, I think it is possible to use only one DATALINK layer for both ICs (or I just need only one SYSREF for FPGA side).

    Do you have any comment?

    Thanks and Regards,

    Trung Nguyen