Two ADRV9009 EVAL Boards on ZCU102

Hi Srimoyi and Tobe,

The given URL just confirms that we can use 2 ADRV9009s on ZCU102, but does not mention about the data synchronization between 2 boards.

In my case, I have built two separated versions - one ADRV9009 on HPC1 , the other on HPC0. Both version works flawlessly. But when combing them to create a version for 2 ADRV9009, it does not work anymore. JESD204 link cannot establish. I am investigating issues may cause this problem.

For data synchronization between 2 boards, I think they should be sourced from a common clock source for device clock and SYSREF. Do you have any further constraint for 2-boards synchronization?

Best Regards,

Trung Nguyen

Please refer USer guide UG 1295 section on RF PLL Phase Synchronization Demo Setup with 2 Two Evaluation Platforms

Hello Vinod,

many thanks for your reference. Somehow I skipped that part.

I would like to ask you some questions regarding the clock scheme.

As in the below picture - UG1295

sysref and refclk (device clock), which are generated from AD9528 of an eval board are provided to all devices.

- As reviewing from the schematic, there is no way to provide SYSREF and REFCLK directly to ADRV9009 from OFFBOARD DEVICES. Signals still have to go through AD9528. That's why I come up with the below clock scheme.

Could you kindly review it?

However, I have some doubts here:

1. What are the input pins for REFCLK on AD9528?

2. How does REFCKL bypass all PLL or logics to reach to ADRV9009?

Since in datasheet of AD9528, there is no such path for REFCLK. There exists a path for SYSREF as in below picture

Thanks in advance,

Trung Nguyen

In this case you can skip the second AD9528 and take out sysref and devclk from first AD9528 via the schematic snapshot you copied above and feed directly to next AD9371.

Any of the 14 outputs of AD9528 can be configured as Refclock