ADRV9008-1 Receiver QEC and RECEIVER DC OFFSET calibration settling time

As per your datasheet ADRV9008-1 Image Rejection spec is given as 75dB with QEC active, within 200 MHz receiver bandwidth.

Also the RECEIVER DC OFFSET (dBFS) value over frequency range is given as >-90dBFS over temperature.

Now when we use ADRV9008-1 hopping requirement and we need to get Receiver Image Rejection spec > 70dB and RECEIVER DC OFFSET (dBFS) >-80 dBFS.

1. What is the QEC calibration approximate settling time required for the frequency range from 100MHz to 3GHz range?

3. We know PLL settling time is around 70uS then what is the approximate minimum settling time need to be given for QEC calibration to achieve above spec over our specified range.

Our Hopping may be anywhere from 100 to 3000 MHz, But we will use 200MHz bandwidth after every hopping frequency.

  • 0
    •  Analog Employees 
    on Jan 3, 2019 9:36 AM over 1 year ago

    What is the frequency by which you want to hop?

    If you are hoping by more than 100MHz then you need to perform QEC and RFDC offset init calibrations which will take approximately 6msec.

    If your hoping frequency is less than 100MHz then only tracking calibrations needs to be run(time required for tracking calibrations is not fixed as it runs continuously to minimize the gain and phase error) for better performance(if you want to achieve an image rejection of 75dBc).


  • Thanks for your detailed response.

    Please confirm our below additional queries,

    1. Since the receiver support instantaneous bandwidth of 200MHz, Then why your are limiting hop frequency above 100MHz to perform QEC and RFDC offset init calibrations?

    2. If QEC and RFDC offset init calibrations will take approximately 6msec to achieve image rejection of 75dBc, Then if we hop after 3mSec instead of waiting upto 6msec, Then how much image rejection (in dBc) is possible in our 3msec calibration time approximately?

  • We have tested your ADRV9009-W/PCBZ eval-board receiver path alone using ZC706 board to measure image rejection and DC offset levels using your TES evaluvation software.

    We are planning to use your device for EW requirement where we have few below observations,

    1. When we give the exact LO frequency as RF (2000MHz CW) from signal generator the signal levels are reduced upto 40dB, I think you DC offset calibration is attenuating our actual signals. How to rectify this?

    2. We have seen the Image rejection in 200MHz Rx BW configuration (at 2000MHz LO) by giving external CW signal from signal generator. When we give a fixed frequency signal the image rejection is below 75dBc. When we sweep the RF frequency from 2001 to 2020MHz at 2004MHz the image rejection goes upto 55dBc.

    3. The 3rd Harmonics is <60dBc is observed when enabling/disabling HD calibration. How to improve the 3rd Harmonics levels below 70dBc? Is it harmonics limitation is due to ADC driver or ADC itself? 

  • 0
    •  Analog Employees 
    on Jan 31, 2019 2:01 PM over 1 year ago in reply to sugu89

    1. Yes. DC Offset calibration treats any time-invariant signal as DC and corrects for it. With the modulated signal to reduce the impact of DC, one option is to Shifting the LO slightly, filtering out the DC leakage and shifting the carrier back using NCO’s in Baseband/FPGA . Again depends upon the bandwidth of your signal.

    2. What is sweep rate/ dwell time?. We manually swept from a signal generator and not seeing any issue.

    If the timing for QEC tracking cals are not met image level will degrade.

    3. Can you please share more details on this? Can you please share a screenshot of receive capture and your config. What's your input signal and level? We are trying to recreate the issue in our lab?

  • 1. DC offset we will try to avoid as per your suggestion.

    2. We are not sweeping at very fast, It was manually changed from one frequency to other frequency in signal generator and changing time may be considered more than 1 second and kept at same frequency for long time.

    We have attached the 999MHz RF input  from sig gen for 1000MHz LO and our fund is -1MHz whereas image +1MHz is <50dBc only. If we change 998MHz the image is improved above 75dBc. This is occurring at randomly not continuously at 999MHz.  Also attached our GUI configuration image.

    3. 3rd Harmonics issues we will comeback with screenshots in details by soon.

  • 0
    •  Analog Employees 
    on Feb 7, 2019 10:19 AM over 1 year ago in reply to sugu89

    2. How long this phenomenon is seen? Is it stuck with 50 dBc for long?

    When you sweep frequency sometimes the image level is 50 dBc and when the QEC converges it goes to 75 dBc.

  • Yes, It is stucked to 50dBc alone and not improving after few minutes until I change it to new frequency in signal generator.

    Also this phenomenon is random not occuring at same spot repeatedly. In total 5 sweep one sweep approximately we are seeing this issue

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  • 0
    •  Analog Employees 
    on Feb 8, 2019 12:17 PM over 1 year ago in reply to sugu89

    This looks strange. 

    I hope while programming the EVB you are turning RF OFF in your signal generator. 

    When it gets stuck, can you try whether turning RF OFF and ON improves?

  • I am unable to understand your above points.

    1. Do you meant to say during device programming or LO programming the input signal to be feed continuously from signal generator for proper QEC calibration?

    2. If yes, How this kind of scenario expected in real-time? during programming input signal should present from antenna is not practical case for ideal QEC calibrations?

    Please try to check in your eval-boards, This issue is coming randomly in many LO frequencies while sweeping the RF signal manually (very slowly).

  • 0
    •  Analog Employees 
    on Feb 11, 2019 9:06 AM over 1 year ago in reply to sugu89

    1. During init cal, there should not be any tone/signal seen at RF Input port. I was asking whether sig gen RF was turned off during init call.

    We tested in our lab and we are not seeing any stuck issue. 

    I hope you are using the latest GUI from our web.

    Can you give the procedure of your testing to reproduce the issue in our lab?

  • We have once again verified the issue and we observed this issue is happening only -5dBFS or above input power levels. When we reduce the power level below -8dBFs we are not seeing this issues.

    Also as per your recommendation we have check the device performance by signal generator OFF condition during device programming or calibration. But still the issue is there when we give signals above -5dBFS. Also this is not suppressed after Power OFF & ON the signal generator output.

    Now please check this phenomenon in your Lab and confirm.

  • 0
    •  Analog Employees 
    on Feb 18, 2019 9:19 AM over 1 year ago in reply to sugu89

    What is the RX gain that you are setting when the signal at RX input is given at -5dBm?With full gain, the maximum input level that the RX path can handle without saturation is -8dBm.

    We tested the same thing in lab and the image levels are always below 75dB.