I have a design with 8 ADRV9009 ICs. AD9528 is the clock chip used and it provide clocks and SYSREF ADRV9009 and the FPGA GT banks. We need all ADRV9009 ICs to have phase sync so the clock inputs must all be aligned.
These 8 ICs are present on one radio card. There are 4 such cards in the system, so the an input GLOBAL CLK is fed into each card.
Below are two possible clocking schemes, which is better/suggested?