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multi-ADRV900x JTAG boundary connections

Category: Hardware
Product Number: ADRV9004

We have a customer looking to add JTAG boundary scan on a dual ADRV9004 design.

ADRV9004 RevA datasheet pg. 95 and Table 19 (pg. 96) seems to be the only info about JTAG - nothing in the UG, rev PrC.  It shows that pins DGPIO_3-11 are used, along with the MODE pin, and these DGPIOs are already deployed in their design. 

So they ask:

1)  Can these DGPIOs simply be branched to the JTAG connector without termination concerns, or is there a preferred way to maintain signal integrity?

2)  What's the best way to connect two devices to the JTAG bus? - e.g. TDI's and TDO's each paralleled or daisy-chained with a TDI--TDO loop, with a TDO--TDI connection between devices?  (These would be the only two devices on the JTAG bus with the connector.)

3)  How do you recommend separating the DGPIOs of each device [for conventional/independent GPIO use] when not in JTAG mode?  Tri-state buffers or switches or ??

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  • Hi Brian, 

    We would recommend maintaining control of the DGPIOs so when they are not being used to do the boundary scan then have them as an input and tie them to ground. This could be done with a switch, JTAG on one side and FPGA on the other with a pull down resistor. Tristate can leave a bit of ambiguity in the off chance that you read and its not ground. With just the two ADRV9004 on the bus then it should be easy enough to daisy chain them.