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ADRV9002 MCS sampling edge



		

			

									
					    br1024
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Sep 26, 2022 
				
			
			
		
    

				
		
    
		    		    
		    
		    		            		        
    Category: Datasheet/Specs
    
    		        		            		    
    Product Number:  ADRV9002 
    
    		        		    		    	
			
    Hi,
    

    In UG-1828 (PrC), it is written "MCS pulse signal will be sampled internally by ADRV9001 by the DEV_CLK signal rising or falling edge.". Does it mean the MCS signal is sampled on both clock edges or only one of them? If only one, how to know the one that will be used, and is there a way to change it?
    

    BR
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      •  Super User  
      
            
			                            
                        
                on Sep 28, 2022 1:40 PM
            
            
					
      
	
      

		
		
      
					
      Hi BR,
      

      There is no way to select the rising or falling Dev_clk edge that is used to sample the MSC pulse. I believe this is a typo and should be just the rising clock edge. All the parts use the same edge so this shouldn't cause any issues with timing or synchronization. The only thing you need to make sure is that you have the adequate timing for the Setup and Hold times.
      

      Regards
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
						
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
        
            
			                            
                        
                on Sep 29, 2022 2:44 PM
            
            
												
						in reply to Ruairí
					
									
        
	
        

		
		
        
					
        Thank you Ruairi.
        

        For the records, the same reference is also made in another sentence of the MCS chapter: "The MCS signal is generated by the external clock chip (for example, AD9528) using device clock DEV_CLK and captured by each ADRV900x device using negative or positive edge of DEV_CLK to meet setup and hold time with good margins."
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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