Post Go back to editing

ADRV9001 LSSI interface clocking

Category: Hardware
Product Number: ADRV9001

Hi Design Support

we are currently trying to fit an ADRV9001 into our design and have found that we are a bit short on diff pairs to implement all LSSI interfaces in 2-Lanes mode if all the control signals are required.

We'd like to drive all channels with the same sample rate (up to 61.44 MHz I/Q) and consider if it is possible to merge or leave out clocks and strobe signals.

Ideally we have only one DCLK, one STROBE, 4x IDATA and 4x QDATA from the FPGA to one ADRV.

Using 4 pairs (DCLK, STROBE, IDATA, QDATA) per rx and tx channel is a bit too much (16 diff pairs) if we use the same sample rate on all 4 channels.

Something in between would be also ok but less diff pair is key.

Do you have any suggestions what to do or to consider?