ADRV9002_Noise floor rise at higher freq

Hello James,

This behavior is to be expected, as you increase the operating frequency you increase the LO Phase Noise. At any operating frequency, the higher the tone power the higher the sideband power will be as well.

The LO phase noise can be optimized/traded off by PLL BW. If your use case is a WB application, you can use smaller PLL BW to get better out of band PLL phase noise.

Let me know if this makes sense!

Best Regards,
Oisín.

Hello James,

This behavior is to be expected, as you increase the operating frequency you increase the LO Phase Noise. At any operating frequency, the higher the tone power the higher the sideband power will be as well.

The LO phase noise can be optimized/traded off by PLL BW. If your use case is a WB application, you can use smaller PLL BW to get better out of band PLL phase noise.

Let me know if this makes sense!

Best Regards,
Oisín.

Hi,

As per your suggestion, PLL bandwidth is reduced from 300KHz to 50KHz. But there is no improvement in the Noise floor  & side band noise at higher freq + High power level. Pls refer the attached FFT images for 300KHz and 50KHz PLL bandwidth configuration. Pls provide your feedback.

Attached FFT data Configuration:
QEC Enable,
AGC Disable
Input Freq: @ 200MHz & 3GHz
PLL Bandwidth: 50KHz & 300KHz
Input Power Level: -10, -70, -80dBm

Here i explain the our application requirement. For Ex: My carrier freq is arrived at 3GHz with -1dBFS power level. If i want to demodulate the 1MHz offset signal from the carrier at -75dBc power level, the 1Mhz offset signal is buried into the noise floor. This analysis is done in the ADC EVM module as well as our module and found the same result. Pls provide your feedback.

Regards

James A

Hello James A,

Our team is currently on Christmas break until Tuesday Jan. 4th 2022. After this break, I will bring your application description to our team, and together we'll get some useful feedback for you.

Until then, we're wishing you a Happy New Year!

Best Regards,
Oisín.

Hello James A,

I brought your issue to another engineer on the team who is quite familiar with this type of blocking experiment. Here are their thoughts:

1. LO phase noise will affect the blocking performance (dBc of the desired signal to blocking) for sure because the reciprocal mixing, higher LO frequency has worse LO phase noise than lower LO frequency which is the nature of LO
2. Similarly with LO, the blocking signal (carrier signal in this case) itself will introduce more noise to desired signal when test from 200Mhz to 3Ghz, customer must make sure the carrier signal phase noise will not limit the test
3. The screenshot showed LTE20M wideband profile is used,
   1. CW “Carrier signal” close to the carrier frequency could mess the DC tracking algorithm
   2. 4096 data capture length is obvious too shot for 30.72Mhz sample rate  

We need to understand  the customer application more to see if ADRV9002 internal LO can meet their blocking performance.

1. What’s the wanted signal bandwidth?  What’s the typical demodulation threshold (SNR) for this signal ?
2. Is this multi carrier system?  Will both the “carrier freq”  and “1Mhz offset signal”   be demodulated in BBIC?

If you can provide us with answers to these concerns and questions, we may be able to determine if your application can be supported using these devices.

Best Regards,
Oisín.

Close this issue due to inactivity.

Best Regards,
Oisín.