ADRV9003 ADC Questions

Greetings;

  This is a follow-up to an answer provided by Michal Bugajski regarding the possible use of the HP ADC vs. the LP ADC.  I have the following questions:

a) are both the LP-ADC and HP-ADC clocked at the same rate during the sampling period?
- if different, please explain why.
b) How does one extract the 5-bit ADC values from the system?
- how are they supposed to be interpreted? Are they MSB or LSB of the 16 bit quality?
- Are these 5 bits "interleaved" some how in the eventual 16 bit I/Q Data stream?
c) Pg: 125, Table 48, calibration bit masks:
D10, D11 - references: "not used when only LP ADC is used"
d) Pg 118, reference to adi_adrv9001_Rx_AdcSwtichEnable_Set()
- when one switches to the 5-bit ADC, how does this change the I/Q data being streamed out of the part?
- is the choice of which ADC to use "exclusive"? (meaning HP OR LP?)
e) does the 5-bit ADC work in a simiar fashion as is described in the AD6676 device? We looked at this, but the fine print said that the ADC is 5 bit only, but provides "a 16-bit representation" of the data.
f) To verify: Does the LP ADC does 16-bit quantization of the input signal

Thank You very much for your time and expertise.

Regards,

Stephen Beckwith

  • Hello,

    The ADC on the AD6676 is a bandpass sigma delta ADC which provides high dynamic range in the user specified IF region and passband.  It achieves this high dynamic range using by oversampling the input signal with a low resolution ADC (17-level flash ADC producing 5-bits) along with quantization noise shaping.   The ADC is followed by digital down conversion and decimation that results in a 16-bit I and Q signal representing the desired passband centered about DC with a IQ data rate equal to FADC/DF where FADC is  the adc clock rate and  DF is the decimation factor.  The datasheet provides more details on the ADC core itself as well as the digital datapath that provides the 16-bit IQ data for the host processor.


    AD6676 (Rev. D) (analog.com)

  • Hello Stephen,

    I'll reply to this question in an attempt to close all your concerns:

    • Both ADC options are clocked at the same rate, as specified by the user's configuration of the part.
    • Users do not have access to the ADC's output, whether configured for the LP or HP variant. The ADC outputs are fed directly into the DFE, where they are post processed and fed to the SSI ports in 16-bit representation. The 5-bits are not interleaved into the 16-bit data, they are post processed in the DFE.
    • I'm not sure which table you're referencing, as it seems you might be using the older revision of the User Guide. If you can find this table in the latest revision of the User Guide I would be happy to provide context on it.
    • Nothing changes on the SSI port, the user will still read the data in exactly the same fashion regardless of which ADC they choose. The choice of HP or LP is exclusive for any one sample. So you can't have both ADCs operating at the same time, however you can swap back and forth between frames.
    • I'm unfamiliar with the AD6676, however it seems that PMH has addressed this question already.
    • The LP ADC does perform 16-bit quantization of the input signal. It is a VCO-Architecture ADC, so a much more straightforward architecture that the Continuous Time Sigma Delta ADC used for the HP ADC.

    I hope this addresses your questions! Let me know if you have any further follow ups.

    Best Regards,
    Oisín.