Is it possible to produce a 40 MHz sample rate using the 38.4 MHz oscillator included on the 9002 development board? If not, how can I determine whether a given external reference clock frequency will be able to produce that sample rate?
In short, the answer is yes, you can produce a 40MHz sample rate using a 38.4 MHz.
If you consult the CLOCK GENERATION AND MULTICHIP SYNCHRONIZATION section of the User Guide, you'll see this:
The reference provided to the ADRV9002 part is used by one of the CLK PLL devices (which one is your choice) to generate a clock that operates on the order of GHz (again, the specific frequency is up to the user). This clk signal is then divided down by a series of Multiplexors and Dividers to provide what is essentially an Arbitrary Sample Rate. Note: there are 'dead zones' in the frequency band where we are unable to provide a stable sampling rate, however these regions are very small. More detail of these 'dead zones' will be given in future revisions of the User Guide.
Under the RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN section of the User Guide, we see this:
Which provides more detail on how the CLK signal is divided down. These multiplexors are controlled by our own API's, the user need only specify a sampling rate and our code will handle the control of each MUX along the path.
I hope this satisfies your question. If you have more questions feel free to respond to this thread.
All the best,