On-board VCXO modification
The AD9371 evaluation board contains an on-board VCXO (Voltage Controlled Crystal Oscillator) as well as the AD9528 chip responsible for the device clock and SYSREF signal generation and distribution. With the hardware configuration provided on the AD9371 evaluation board, a user can generate device clock frequencies such as 122.88MHz, 153.6MHz, 184.32MHz, 245.76MHz, and 307.2MHz.
There are limitations with the default hardware configuration in the scenario where a user desired device frequencies are not related to the on-board 122.88MHz VCXO by a rational fraction. Examples of such device clock frequency are: 125MHz, 133.33MHz, 250MHz and 266.66MHz. The paragraph below outlines these limitations as well as explains how they can be overcome with an AD9371 evaluation board hardware modification.
AD9528 description
The AD9528 contains two cascaded PLL stages. The first PLL called PLL1 is configured to work with a narrow loop filter bandwidth. PLL1 provides jitter clean-up of the input reference signal ((CPRI clock for example) to provide a clean clock for the input stage of PLL2. The configuration of PLL2 is described in Figure 1.
PLL2 blocks are programmable and the user can select values of:
• M1 = 3,4 or 5
• N2 = 1, 2, 3, …, 256
• R1 = 0.5, 1, 2, …, 31
• chDIV = 1, 2, 3, …, 256
Limitations:
• The PLL2 VCO frequency operates in range from 3450MHz to 4025MHz.
• Maximum frequency after the channel divider is limited to 1250 MHz for OUT1,OUT2 and all other OUT is 1000MHz.
In order to calculate AD9371 DEV_CLK frequency the user should follow equations outlined below:
Note that VCO can operate with frequency range from 3450MHz to 4025MHz.
AD9528 operation examples
The AD9528 can generate different DEV_CLK frequencies from the VCXO frequency only when the ratio of the two frequencies is a rational fraction. If the result of division of DEV_CLK and VCXO frequency does not create a rational fraction then the AD9528 cannot precisely generate the desire DEV_CLK.
Below are some examples of how DEV_CLK is calculated based on an on-board VCXO with a frequency of 122.88 MHz.
The AD9371 evaluation board supports two different footprints for the on-board VCXO. Figure 2 outlines two different VCXO symbols present in the AD9371 evaluation board schematic. Both footprint details are outlined in Figure 3 and Figure 4
VCXO recommendations
The AD9371 evaluation board utilizes a VCXO manufactured by Crystek Corporation. All frequency variants recommended for AD9371
evaluation board are based on the Crystek Corporation VCXO series CVHD-950.
Below are typical characteristics of CVHD-950 series VCXO:
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From the AD9528 data sheet:
M1 = 3,4,5
Also it appears from the diagrams Figs 27 & 30 that the x 2 multiplier is in series with the 5 bit divider. it appears (Table 50) that this can be enabled with any value of R1 divider, If this is true then additional dividers possible are:
0.5, 1.5, ... 15.5
Finally, regarding the requirement
Maximum frequency after the RF VCO divider (M1) is limited to 1000MHz
I don't find any such limitation in the data sheet. I do see (Table 8)
Output Frequency 1000MHz or 1250MHz otuputs 1 and 2 only
However output is after channel divider. is it possible that the channel divider will work with input < 1250MHz
Please verify
Thanks
Paul