Where can I get links for AD9375 user guide, Schematics and other design files?
- http://www.analog.com/en/design-center/landing-pages/001/integrated-rf-agile-transceiver-design-resources.html
- http://www.analog.com/en/design-center/landing-pages/001/transceiver-evaluation-software.html
- What all will be in package when I order ADRV9375-N/PCBZ board?
- ADRV9375-N/PCBZ radio card
- SKY66297 power amplifier (PA) evaluation card
- Two 8GB SD cards
- One for Linux driver and IIO Scope (AD-FMC-SDCARD)
- One for Windows-based GUI (ADRV9371-SDCARD)
What is the max power and Bandwidth supported by AD9375 DPD?
- Max power at PA output is 5 W to 10 W but depends on the PA, it is defined at PA output as the frontend losses varies with design.
- 40 MHz instantaneous BW is supported.
What should be the PA requirements to get maximum linearization with AD9375 DPD?
- GaAs and LDMOS Doherty PAs are best suited for DPD.
- Below are few PA RAW requirements that have shown to give good results in the past
- RAW ACLR – better than -30 dBc at rated output power is usually a good starting point
- VBW – 3x the Instantaneous signal BW
- ORX flatness – minimal ripples expected. refer user guide
- PA flatness – minimal ripples expected. refer user guide
What typical performance of AD9375 DPD can be expected?
- Efficiency: It depends on the PA selected, operating point of PA, and performance target of the system.
- ACLR: for most PAs, typically 15 to 20 dB correction in ACLR
Are there any recommended PAs for AD9375 DPD
- Yes, Skyworks and NXP are preferred PA vendors. Please refer http://www.analog.com/en/applications/technology/sdr-radioverse-pavilion-home/wideband-transceivers/digital-pre-distortion.html for a list of tested PAs and test reports.
Do customer need to pay for the DPD algorithm?
- No, it comes built into the AD9375 and is a tracking calibration similar to TxQEC or TxLOL.
Is AD9375 pin compatible with AD9371? What is the difference between AD9371 and AD9375 apart from DPD?
- Yes, It has VSWR measurement and CLGC (Closed Loop Gain Control) capabilities.
For Evaluation purposes, in order to complete the setup, we need RF cables and Couplers. Does ADI has any guidelines/ Recommendation for same?
- There are no specific recommendations and guidelines. One thing to make sure is frequency range and Power handling capability of cable and coupler while selecting.
- Please refer the User Guide UG-992 for a typical DPD bench setup.
What are the things that need to be taken care in order to prevent PA damage while running DPD for first time?
- Make sure to turn off the PA while programming the device.
- Start with lower power (high TX attenuation) and then slowly increase the TX power (decrease TX attenuation) to get required rated output.
What are the advantages of having an integrated DPD transceiver?
- The number of SerDes lanes required between the FPGA and transceiver is reduced.
- Expensive FPGAs with DPD IP can be traded off for a cheaper FPGA option.
- As the DPD and JESD lane requirements for an FPGA are eliminated or reduced, the power consumed by the FPGA (and, therefore, the system) is also reduced.
- The above advantages also result in reduced system cost.
Thus, overall SWaP-C (Size Weight and Power – Cost) is reduced with the use of the AD9375.