AD9375 DPD using SW v5.2.2

Can you please test by using the below GUI and see if the problem persists?

DPD GUI for AD9375

We have the AD9375 integrated into our baseband unit.

The issue we are experiencing is not in the eval board but it is in our unit. 

Is this issue seen randomly or are you seeing this issue only during power ramp up time? By power rampup time, do you mean TX input signal ramp up time after TX path enable trigger?

Are you running DPD init and tracking cal? Can you share with us the software sequence?

Are you configuring the chip in TDD mode or FDD mode? Can you try in FDD mode and check if you are seeing the same issue?

Is this issue seen randomly or are you seeing this issue only during power ramp up time?  

                The issue is not random.  It can be observed all the time.   If we force TX Enable to high before the test waveform is sent, the DPD seems to work fine.   It appears that if the power ramp is seen by DPD, the correction never works (even if we keep TX Enable high all the time). 

By power ramp up time, do you mean TX input signal ramp up time after TX path enable trigger?

                In the TDD system, TX Enable is used to enable the Power Amplifier biasing.   TX Enable timing is adjusted to make sure that PA is fully biased when the RF signal is transmitted

Are you running DPD init and tracking cal? Can you share with us the software sequence?

The sequence is as follows:

1.  Set Tx frequency: MYKONOS_setRfPllFrequency(TX_PLL)
2. Turn PA off and Mykonos off
3. mykonos_runInitCals(calMask= Tx QEC Init | LoopBack Rx LO Delay | LoopBack Rx Rx QEC Init | Rx LO Delay | Rx QEC Init)
4. Turn PA on, set tx power and att from calibration table
5. mykonos_runInitCals(calMask= DPD Init | CLGC_INIT | VSWR Init)
6.  Set Rx frequency: MYKONOS_setRfPllFrequency(RX_PLL)
7. Turn PA off and Mykonos off
8. mykonos_runInitCals(calMask= Tx QEC Init | LoopBack Rx LO Delay | LoopBack Rx Rx QEC Init | Rx LO Delay | Rx QEC Init)
9. Turn PA on,  set rx power and att from calibration table
10. mykonos_runInitCals(calMask= DPD Init | CLGC_INIT | VSWR Init)
11. Set tx power to -150
12. Deactivate CFR
13. MYKONOS_setRfPllFrequency(TX_PLL | RX_PLL)
14. Mykonos initialisation sequence (mykonos_resetDevice, mykonos_initialize(enableDpdDataPath))
15. Mykonos CLkPLL status check
16. Mykonos load ARM file
17. MYKONOS_setRfPllFrequency(TX_PLL)
18. MYKONOS_setRfPllFrequency(RX_PLL)
19. MYKONOS_setRfPllFrequency(SNIFFER)
20. Mykonos_configDpd
21. Mykonos_setGpio
22. Mykonos config temp sensors
23. Mykonos set manual gain 
24. Mykonos_setTx1lAttenuation(att=0)
25. Turn PA off
26. mykonos_runInitCals(calMask= all flag on)
27. Turn PA on
28. Mykonos_runInitCals(calMask= DPD Init | CLGC_INIT | VSWR Init)
29. Mykonos_enableTrackingCals (DPD on)
30. mykonos_radioOn
31. mykonos_setObsRxPathSource(OBS_RxOFF)
32. mykonos_setObsRxPathSource(OBS_INTERNALCALS)
33. mykonos_radioOff
34. Activate CFR

Are you configuring the chip in TDD mode or FDD mode? Can you try in FDD mode and check if you are seeing the same issue?

The chip is configured in FDD mode.

Thanks.

ChrisM said:

 If we force TX Enable to high before the test waveform is sent, the DPD seems to work fine.   It appears that if the power ramp is seen by DPD, the correction never works (even if we keep TX Enable high all the time). 

Generally, the correct sequence is to pull the TX_EN high and then transmit RF signal. What is your application and why do you want to feed the signal before TX ON?

Are you testing with TDD signal, with the chip in FDD mode?

Can you try the testing with 3dB lower power going into the TX input? This way we can make sure that the PA is not driven into compression.

Can you share with us your DPD configuration parameters and DPD statistics?