Post Go back to editing

AD9375 TX Image (LO Frequency - Message Frequency) Leakage

Category: Hardware

I am using AD9375 to generate RF Signal and AD9528 as Clock Synthesizer 

AD9375 is interfaced with Xilinx FPGA - XCZU11EG - 1FFVC1156I and set to DDS Single Tone

The clock used is 122.88MHz; LO - 2GHz and MSG - 10 MHz. Lane Rate - 4915.200 MHz

We have done all initial calibrations suggested by User Guide - 992 such as TX QEC and TX LOL and it is done successfully which is attached below:

Please wait...
AD9528_initialize Done.
rx_clkgen: MMCM-PLL locked (122880000 Hz)
tx_clkgen: MMCM-PLL locked (122880000 Hz)
rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
MCS successful
CLKPLL locked
AD9371 ARM version 5.2.2
PLLs locked
Calibrations completed successfully
tx_adxcvr: OK (4915200 kHz)
rx_adxcvr: OK (4915200 kHz)
rx_os_adxcvr: OK (4915200 kHz)
RxFramerStatus = 0x20
DeframerStatus = 0x68
rx_jesd status:
        Link is enabled
        Measured Link Clock: 122.881 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 3.840 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_jesd lane 0 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: No
rx_jesd lane 1 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: No
tx_jesd status:
        Link is enabled
        Measured Link Clock: 122.881 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 7.680 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 122.881 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 7.680 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd lane 0 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 60 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x43, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
rx_os_jesd lane 1 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 61 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x44, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
tx_dac: Successfully initialized (245761108 Hz)
rx_adc: Successfully initialized (122875976 Hz)
rx_obs_adc: Successfully initialized (245751953 Hz)
Done

Even though, we are able to see both (LO+ MSG) and (LO-MSG) at the same power Level

                                             

Kindly provide suggestions to eliminate this Image Frequency, as the image Power Level is above the datasheet Specs

  • Can you check the PLL lock status using the API  MYKONOS_checkPllsLockStatus() .

    What is the reference clock frequency given ? Is the reference clock locked and stable. ?
    Is the reference clock frequency matching with the device clock frequency in you init files ? 
    Check if tracking cals are enabled or not by reading back the status using MYKONOS_getEnabledTrackingCals().
    Can you check the LOL and the QEC tracking cal status( Iteration count and update count over time) using the API  MYKONOS_getTxQecStatus()? Check if the update count is increasing with time, which means that the cal is running.