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AD9375 and AD9528 Design Review Support

Dear Support Team,

We are using AD9375 and AD9528 in our design. We have interfaced 4 AD9375 chips with Xilinx Zynq US+MPSoC(XCZU11EG). 

AD9375 IC 1 & 2: One Tx & One ORx channel  is used operating at 4.4GHz to 5GHz ; Tx IQ Rate: 245.76MSPS & ORx IQ Rate: 122.88 MHz

AD9375 IC 3 & 4: Two Rx channels are used operating at 4.4GHz to 5GHz; Rx IQ Rate: 122.88 MHz

AD9528 Clock Synthesiser inputs: VCXO 122.88MHz and OCXO 10MHz 10ppb Reference Clock used to generate 122.88MHz Device Clock and 960KHz Sysref clocks.

JESD204B interface is connected to GTH Bank of MPSoC. 4 GTH Banks are used. Two GTH Banks share single Reference clocks. Attached Clock Tree in the schematic.

Two LTM4644 Switching Regulator is used to power all 4 AD9375 chips.

Please find attached Schematic Design. Please review the design and provide your feedback.

PDF